diff --git a/docs/guide.rst b/docs/guide.rst index 551250ff..43fb7470 100644 --- a/docs/guide.rst +++ b/docs/guide.rst @@ -99,5 +99,5 @@ SLEIGH & P-Code References -------------------------- Extensive documentation covering SLEIGH and P-Code is available online: -* `SLEIGH, P-Code Introduction `_ -* `P-Code Reference Manual `_ \ No newline at end of file +* `SLEIGH, P-Code Introduction `_ +* `P-Code Reference Manual `_ \ No newline at end of file diff --git a/docs/index.rst b/docs/index.rst index 355003ef..dd5ae381 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,7 +1,7 @@ pypcode documentation ===================== pypcode is a machine code disassembly and IR translation library for Python using the -excellent `SLEIGH `__ library from the `Ghidra `__ framework (version 11.4.2). +excellent `SLEIGH `__ library from the `Ghidra `__ framework (version 12.0.1). This library was created primarily for use with `angr `__, which provides analyses and symbolic execution of p-code. diff --git a/pypcode/processors/68000/data/languages/68000.sinc b/pypcode/processors/68000/data/languages/68000.sinc index 9ad6a661..674c9d06 100644 --- a/pypcode/processors/68000/data/languages/68000.sinc +++ b/pypcode/processors/68000/data/languages/68000.sinc @@ -101,6 +101,7 @@ define token instr (16) op5 = (5,5) op7 = (7,7) op8 = (8,8) + op10 = (10,10) op11 = (11,11) quick = (9,11) op811 = (8,11) @@ -258,6 +259,7 @@ define token bdisp32 (32) bd32 = (0,31) signed; define token odisp16 (16) od16 = (0,15) signed; define token odisp32 (32) od32 = (0,31) signed; define token fldparm (16) + fldpar=(0,15) flddo=(11,11) fldoffdat=(6,10) fldoffreg=(6,8) @@ -588,6 +590,12 @@ f_wd: fldwdreg is flddw=1 & fldwdreg { export fldwdreg; } rreg: regxdn is da=0 & regxdn { export regxdn; } rreg: regxan is da=1 & regxan { export regxan; } +regPlus: (regan)+ is regan { export regan; } +regxPlus: (regxan)+ is regxan { export regxan; } +reg9Plus: (reg9an)+ is reg9an { export reg9an; } +regParen: (regan) is regan { export regan; } +d32l: (d32)".l" is d32 { export *[const]:4 d32; } + # Condition codes cc: "t" is op811=0 { export 1:1; } @@ -875,8 +883,8 @@ macro rotateRightExtended(count, register, width) { VF = 0; } -:^instruction is extGUARD=0 & mode2 & reg9an & mode & regan & instruction - [ extGUARD=1; regtfan=regan; savmod1=mode; regtsan=reg9an; savmod2=mode2; ] {} +:^instruction is extGUARD=0 & mode2 & reg9an & mode & regan & instruction + [ extGUARD=1; regtfan=regan; savmod1=mode; regtsan=reg9an; savmod2=mode2; ] {} # Here are the instructions @@ -1043,7 +1051,8 @@ with : extGUARD=1 { local source = regdn; mask:4 = 1 << (const8 & 31); ZF = (source & mask) == 0; regdn = source & (~mask); } -:bfchg e2l{f_off:f_wd} is opbig=0xea & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +bfOffWd: {f_off:f_wd} is f_off & f_wd { } +:bfchg e2l^bfOffWd is opbig=0xea & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); @@ -1053,7 +1062,7 @@ with : extGUARD=1 { e2l = (tmp & ~mask) | (~(tmp & mask) & mask); } -:bfclr e2l{f_off:f_wd} is opbig=0xec & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +:bfclr e2l^bfOffWd is opbig=0xec & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); @@ -1063,7 +1072,7 @@ with : extGUARD=1 { e2l = tmp & ~mask; } -:bfexts e2l{f_off:f_wd},f_reg is opbig=0xeb & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +:bfexts e2l^bfOffWd,f_reg is opbig=0xeb & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); tmp:4 = e2l; tmp = tmp << f_off; @@ -1073,7 +1082,7 @@ with : extGUARD=1 { resbitflags(tmp2, f_wd-1); } -:bfextu e2l{f_off:f_wd},f_reg is opbig=0xe9 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +:bfextu e2l^bfOffWd,f_reg is opbig=0xe9 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); @@ -1081,7 +1090,7 @@ with : extGUARD=1 { resbitflags(tmp, f_wd-1); } -:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg & flddo=0 & fldoffdat=0 & flddw=0 & fldwddat=0; e2l +:bfffo e2l^bfOffWd,f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg & flddo=0 & fldoffdat=0 & flddw=0 & fldwddat=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { # "Find First One in Bit Field" pronounced "boo-foe" # Set the destination f_reg with the position of the first 1 bit in the source e2l. @@ -1096,7 +1105,7 @@ with : extGUARD=1 { f_reg = zext(tmp != 0) * lzcount(tmp); } -:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg ; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +:bfffo e2l^bfOffWd,f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg ; e2l [ savmod2=savmod1; regtsan=regtfan; ] { local tmp:4 = e2l; tmp = (tmp << f_off) >> (32 - f_wd); tmp = (tmp << (32 - f_wd)); @@ -1109,7 +1118,7 @@ with : extGUARD=1 { } -:bfins f_reg,e2l{f_off:f_wd} is opbig=0xef & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +:bfins f_reg,e2l^bfOffWd is opbig=0xef & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); mask:4 = 0; bitmask(mask, f_wd); @@ -1119,7 +1128,7 @@ with : extGUARD=1 { e2l = (e2l & ~mask) | (tmp << (32 - f_off - f_wd)); } -:bfset e2l{f_off:f_wd} is opbig=0xee & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +:bfset e2l^bfOffWd is opbig=0xee & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); @@ -1129,7 +1138,7 @@ with : extGUARD=1 { e2l = e2l & ~mask; } -:bftst e2l{f_off:f_wd} is opbig=0xe8 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { +:bftst e2l^bfOffWd is opbig=0xe8 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { logflags(); tmp:4 = e2l; getbitfield(tmp, f_off, f_wd); @@ -1204,180 +1213,183 @@ define pcodeop callm; } #TODO: should constrain CAS to ignore mode=7 & regan=4 (place CAS2 before CAS to avoid problem) -:cas2.w regdcw:regdc2w,regduw:regdu2w,(regda):(regda2) is op015=0x0cfc; regda & ext_911=0 & regduw & ext_35=0 & regdcw; regda2 & ext2_911=0 & regdu2w & ext2_35=0 & regdc2w { - dc1:4 = zext(regdcw); - dc2:4 = zext(regdc2w); - if(dc1!=regda) goto ; - if(dc2!=regda2) goto ; - regda = zext(regduw); - regda2 = zext(regdu2w); - ZF = 1; - NF = 0; - goto inst_next; - - regdcw = regda(2); - regdc2w = regda2(2); - ZF = 0; - NF = 1; -} -:cas2.l regdc:regdc2,regdu:regdu2,(regda):(regda2) is op015=0x0efc; regda & ext_911=0 & regdu & ext_35=0 & regdc; regda2 & ext2_911=0 & regdu2 & ext2_35=0 & regdc2 { - if(regdc!=regda) goto ; - if(regdc2!=regda2) goto ; - regda = regdu; - regda2 = regdu2; - ZF = 1; - NF = 0; - goto inst_next; - - regdc = regda; - regdc2 = regda2; - ZF = 0; - NF = 1; -} - -:cas.b regdcb,regdub,e2b is opbig=0x0a & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdub & ext_35=0 & regdcb; e2b [ savmod2=savmod1; regtsan=regtfan; ] { - local tmp = e2b; - if(tmp==regdcb) goto ; - regdcb = tmp; - ZF = 0; - NF = 1; - goto inst_next; - - e2b = regdub; - ZF = 1; - NF = 0; -} -:cas.w regdcw,regduw,e2w is opbig=0x0c & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regduw & ext_35=0 & regdcw; e2w [ savmod2=savmod1; regtsan=regtfan; ] { - local tmp = e2w; - if(tmp==regdcw) goto ; - regdcw = tmp; - ZF = 0; - NF = 1; - goto inst_next; - - e2w = regduw; - ZF = 1; - NF = 0; -} -:cas.l regdc,regdu,e2l is opbig=0x0e & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdu & ext_35=0 & regdc; e2l [ savmod2=savmod1; regtsan=regtfan; ] { - local tmp = e2l; - if(tmp==regdc) goto ; - regdc = tmp; - ZF = 0; - NF = 1; - goto inst_next; - - e2l = regdu; - ZF = 1; - NF = 0; +:cas2.w regdcw:regdc2w,regduw:regdu2w,(regda):(regda2) is op015=0x0cfc; regda & ext_911=0 & regduw & ext_35=0 & regdcw; regda2 & ext2_911=0 & regdu2w & ext2_35=0 & regdc2w { + dc1:4 = zext(regdcw); + dc2:4 = zext(regdc2w); + if(dc1!=regda) goto ; + if(dc2!=regda2) goto ; + regda = zext(regduw); + regda2 = zext(regdu2w); + ZF = 1; + NF = 0; + goto inst_next; + + regdcw = regda(2); + regdc2w = regda2(2); + ZF = 0; + NF = 1; +} + +:cas2.l regdc:regdc2,regdu:regdu2,(regda):(regda2) is op015=0x0efc; regda & ext_911=0 & regdu & ext_35=0 & regdc; regda2 & ext2_911=0 & regdu2 & ext2_35=0 & regdc2 { + if(regdc!=regda) goto ; + if(regdc2!=regda2) goto ; + regda = regdu; + regda2 = regdu2; + ZF = 1; + NF = 0; + goto inst_next; + + regdc = regda; + regdc2 = regda2; + ZF = 0; + NF = 1; +} + +:cas.b regdcb,regdub,e2b is opbig=0x0a & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdub & ext_35=0 & regdcb; e2b [ savmod2=savmod1; regtsan=regtfan; ] { + local tmp = e2b; + if(tmp==regdcb) goto ; + regdcb = tmp; + ZF = 0; + NF = 1; + goto inst_next; + + e2b = regdub; + ZF = 1; + NF = 0; +} + +:cas.w regdcw,regduw,e2w is opbig=0x0c & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regduw & ext_35=0 & regdcw; e2w [ savmod2=savmod1; regtsan=regtfan; ] { + local tmp = e2w; + if(tmp==regdcw) goto ; + regdcw = tmp; + ZF = 0; + NF = 1; + goto inst_next; + + e2w = regduw; + ZF = 1; + NF = 0; +} + +:cas.l regdc,regdu,e2l is opbig=0x0e & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdu & ext_35=0 & regdc; e2l [ savmod2=savmod1; regtsan=regtfan; ] { + local tmp = e2l; + if(tmp==regdc) goto ; + regdc = tmp; + ZF = 0; + NF = 1; + goto inst_next; + + e2l = regdu; + ZF = 1; + NF = 0; } :chk.w eaw,reg9dnw is (op=4 & reg9dnw & op68=6 & $(DAT_ALTER_ADDR_MODES))... & eaw { - build eaw; - local address:4 = zext(eaw); - local bound:2 = *:2 address; - local signed_bound:4 = sext(bound); - local signed_register:4 = sext(reg9dnw); + build eaw; + local address:4 = zext(eaw); + local bound:2 = *:2 address; + local signed_bound:4 = sext(bound); + local signed_register:4 = sext(reg9dnw); - if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next; - NF = signed_register s< 0; - __m68k_trap(6:1); + if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next; + NF = signed_register s< 0; + __m68k_trap(6:1); } :chk.l eal,reg9dn is (op=4 & reg9dn & op68=4 & $(DAT_ALTER_ADDR_MODES))... & eal { - build eal; - local address:4 = zext(eal); - local bound:4 = *:4 address; - local signed_bound:4 = sext(bound); - local signed_register:4 = sext(reg9dn); + build eal; + local address:4 = zext(eal); + local bound:4 = *:4 address; + local signed_bound:4 = sext(bound); + local signed_register:4 = sext(reg9dn); - if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next; - NF = signed_register s< 0; - __m68k_trap(6:1); + if ((signed_register s>= 0) && (signed_register s<= signed_bound)) goto inst_next; + NF = signed_register s< 0; + __m68k_trap(6:1); } :chk2.b e2b,rreg is opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2b [ savmod2=savmod1; regtsan=regtfan; ] { - build e2b; - local address:4 = zext(e2b); - local lower:1 = *:1 address; - local upper:1 = *:1 (address + 1); - local signed_lower:4 = sext(lower); - local signed_upper:4 = sext(upper); - local signed_register:4 = sext(rreg); + build e2b; + local address:4 = zext(e2b); + local lower:1 = *:1 address; + local upper:1 = *:1 (address + 1); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); - ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); - CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); - if (!CF) goto inst_next; - __m68k_trap(6:1); + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + if (!CF) goto inst_next; + __m68k_trap(6:1); } :chk2.w e2w,rreg is opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2w [ savmod2=savmod1; regtsan=regtfan; ] { - build e2w; - local address:4 = zext(e2w); - local lower:2 = *:2 address; - local upper:2 = *:2 (address + 2); - local signed_lower:4 = sext(lower); - local signed_upper:4 = sext(upper); - local signed_register:4 = sext(rreg); + build e2w; + local address:4 = zext(e2w); + local lower:2 = *:2 address; + local upper:2 = *:2 (address + 2); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); - ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); - CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); - if (!CF) goto inst_next; - __m68k_trap(6:1); + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + if (!CF) goto inst_next; + __m68k_trap(6:1); } :chk2.l e2l,rreg is opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=1; e2l [ savmod2=savmod1; regtsan=regtfan; ] { - build e2l; - local address:4 = zext(e2l); - local lower:4 = *:4 address; - local upper:4 = *:4 (address + 4); - local signed_lower:4 = sext(lower); - local signed_upper:4 = sext(upper); - local signed_register:4 = sext(rreg); + build e2l; + local address:4 = zext(e2l); + local lower:4 = *:4 address; + local upper:4 = *:4 (address + 4); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); - ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); - CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); - if (!CF) goto inst_next; - __m68k_trap(6:1); + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + if (!CF) goto inst_next; + __m68k_trap(6:1); } :cmp2.b e2b,rreg is opbig=0 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2b [ savmod2=savmod1; regtsan=regtfan; ] { - build e2b; - local address:4 = zext(e2b); - local lower:1 = *:1 address; - local upper:1 = *:1 (address + 1); - local signed_lower:4 = sext(lower); - local signed_upper:4 = sext(upper); - local signed_register:4 = sext(rreg); + build e2b; + local address:4 = zext(e2b); + local lower:1 = *:1 address; + local upper:1 = *:1 (address + 1); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); - ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); - CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); } :cmp2.w e2w,rreg is opbig=2 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2w [ savmod2=savmod1; regtsan=regtfan; ] { - build e2w; - local address:4 = zext(e2w); - local lower:2 = *:2 address; - local upper:2 = *:2 (address + 2); - local signed_lower:4 = sext(lower); - local signed_upper:4 = sext(upper); - local signed_register:4 = sext(rreg); + build e2w; + local address:4 = zext(e2w); + local lower:2 = *:2 address; + local upper:2 = *:2 (address + 2); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); - ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); - CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); } :cmp2.l e2l,rreg is opbig=4 & op67=3 & $(CTL_ADDR_MODES); rreg & wl=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { - build e2l; - local address:4 = zext(e2l); - local lower:4 = *:4 address; - local upper:4 = *:4 (address + 4); - local signed_lower:4 = sext(lower); - local signed_upper:4 = sext(upper); - local signed_register:4 = sext(rreg); + build e2l; + local address:4 = zext(e2l); + local lower:4 = *:4 address; + local upper:4 = *:4 (address + 4); + local signed_lower:4 = sext(lower); + local signed_upper:4 = sext(upper); + local signed_register:4 = sext(rreg); - ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); - CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); + ZF = ((signed_register == signed_lower) || (signed_register == signed_upper)); + CF = !((signed_register s>= signed_lower) && (signed_register s<= signed_upper)); } @ifdef MC68040 @@ -1388,7 +1400,7 @@ cachetype: "instr" is op67=2 { export 2:4; } cachetype: "both" is op67=3 { export 3:4; } :cinvl cachetype,(regan) is opbig=0xf4 & cachetype & op5=0 & op34=1 & regan { invalidateCacheLines(cachetype, regan); } :cinvp cachetype,(regan) is opbig=0xf4 & cachetype & op5=0 & op34=2 & regan { invalidateCacheLines(cachetype, regan); } -:cinva cachetype is opbig=0xf4 & cachetype & op5=0 & op34=3 { invalidateCacheLines(cachetype); } +:cinva cachetype is opbig=0xf4 & cachetype & op5=0 & op34=3 { invalidateCacheLines(cachetype); } @endif # MC68040 @@ -1397,13 +1409,13 @@ cachetype: "both" is op67=3 { export 3:4; } :cpushl cachetype,(regan) is opbig=0xf4 & cachetype & op5=1 & op34=1 & regan {pushInvalidateCaches(cachetype, regan);} :cpushp cachetype,(regan) is opbig=0xf4 & cachetype & op5=1 & op34=2 & regan {pushInvalidateCaches(cachetype, regan);} -:cpusha cachetype is opbig=0xf4 & cachetype & op5=1 & op34=3 {pushInvalidateCaches(cachetype);} +:cpusha cachetype is opbig=0xf4 & cachetype & op5=1 & op34=3 {pushInvalidateCaches(cachetype);} @endif # MC68040 -:clr.b eab is (opbig=0x42 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = 0; NF=0; ZF=1; VF=0; CF=0; } -:clr.w eaw is (opbig=0x42 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { eaw = 0; NF=0; ZF=1; VF=0; CF=0; } -:clr.l eal is (opbig=0x42 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { eal=0; NF=0; ZF=1; VF=0; CF=0; } +:clr.b eab is (opbig=0x42 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = 0; NF=0; ZF=1; VF=0; CF=0; } +:clr.w eaw is (opbig=0x42 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { eaw = 0; NF=0; ZF=1; VF=0; CF=0; } +:clr.l eal is (opbig=0x42 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { eal=0; NF=0; ZF=1; VF=0; CF=0; } :cmp.b eab,reg9dnb is (op=11 & reg9dnb & op68=0)... & eab { o2:1=eab; subflags(reg9dnb,o2); local tmp =reg9dnb-o2; resflags(tmp); } :cmp.w eaw,reg9dnw is (op=11 & reg9dnw & op68=1)... & eaw { o2:2=eaw; subflags(reg9dnw,o2); local tmp =reg9dnw-o2; resflags(tmp); } @@ -1417,25 +1429,26 @@ cachetype: "both" is op67=3 { export 3:4; } :cmpi.w const16,e2w is opbig=12 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { o2:2=e2w; subflags(o2,const16); local tmp =o2-const16; resflags(tmp);} :cmpi.l const32,e2l is opbig=12 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { o2:4=e2l; subflags(o2,const32); local tmp =o2-const32; resflags(tmp);} -:cmpm.b (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=0 & op5=0 & op34=1 & regan { local tmp1=*:1 regan; regan=regan+1; local tmp2=*:1 reg9an; reg9an=reg9an+1; - subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } -:cmpm.w (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=1 & op5=0 & op34=1 & regan { local tmp1=*:2 regan; regan=regan+2; local tmp2=*:2 reg9an; reg9an=reg9an+2; - subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } -:cmpm.l (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=2 & op5=0 & op34=1 & regan { local tmp1=*:4 regan; regan=regan+4; local tmp2=*:4 reg9an; reg9an=reg9an+4; - subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } +:cmpm.b regPlus,reg9Plus is op=11 & reg9Plus & op8=1 & op67=0 & op5=0 & op34=1 & regPlus { local tmp1=*:1 regPlus; regPlus=regPlus+1; local tmp2=*:1 reg9Plus; reg9Plus=reg9Plus+1; + subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } +:cmpm.w regPlus,reg9Plus is op=11 & reg9Plus & op8=1 & op67=1 & op5=0 & op34=1 & regPlus { local tmp1=*:2 regPlus; regPlus=regPlus+2; local tmp2=*:2 reg9Plus; reg9Plus=reg9Plus+2; + subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } +:cmpm.l regPlus,reg9Plus is op=11 & reg9Plus & op8=1 & op67=2 & op5=0 & op34=1 & regPlus { local tmp1=*:4 regPlus; regPlus=regPlus+4; local tmp2=*:4 reg9Plus; reg9Plus=reg9Plus+4; + subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } # cpBcc # need to know specific copressors use copcc1 # cpDBcc # use copcc2 # cpGEN # cpScc # use copcc2 # cpTRAPcc # use copcc2 -:db^cc regdnw,addr16 is op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16 { +:db^cc regdnw,addr16 is op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16 +{ if (cc) goto inst_next; regdnw=regdnw-1; if (regdnw!=-1) goto addr16; } -:divs.w eaw,reg9dn is (op=8 & reg9dn & op68=7)... & eaw { +:divs.w eaw,reg9dn is (op=8 & reg9dn & op68=7)... & eaw { local denom = sext(eaw); local divis = reg9dn; local div = divis s/ denom; @@ -1444,15 +1457,17 @@ cachetype: "both" is op67=3 { export 3:4; } resflags(div); reg9dn = (rem << 16) | (div & 0xffff); } - -:divu.w eaw,reg9dn is (op=8 & reg9dn & op68=3)... & eaw { + +:divu.w eaw,reg9dn is (op=8 & reg9dn & op68=3)... & eaw +{ local denom = zext(eaw); local divis = reg9dn; local div = divis / denom; local rem = divis % denom; CF=0; resflags(div); - reg9dn = (rem << 16) | (div & 0xffff); } + reg9dn = (rem << 16) | (div & 0xffff); + } #remyes: "s" is regdq & (regdr=regdq) & divsgn=1 { } remyes: "sl" is divsgn=1 { } @@ -1464,7 +1479,7 @@ remyes: "ul" is divsgn=0 { } # NB- Need to be very careful with div to not clobber when regdr and regdq refer to the same reg. # When this happens it seems the destination reg should get the quotient, not the remainder. # -subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=0 { +subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=0 { local divis = regdq; local denom = glbdenom; local rem = divis % denom; @@ -1486,7 +1501,7 @@ subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=0 { #subdiv: regdq is regdq & regdr=regdq & divsz=0 & divsgn=1 { regdq = regdq s/ glbdenom; export regdq; } -subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=1 { +subdiv: regdr:regdq is regdq & regdr & divsz=0 & divsgn=1 { local divis = regdq; local denom = glbdenom; local rem = divis s% denom; @@ -1534,31 +1549,34 @@ subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=1 { :extb.l regdn is op=4 & reg9dn=4 & op68=7 & op35=0 & regdn { local tmp = regdn:1; regdn = sext(tmp); resflags(regdn); logflags(); } @ifdef COLDFIRE -:halt is d16=0x4ac8 unimpl +:halt is d16=0x4ac8 unimpl @endif -:illegal is d16=0x4afc unimpl +:illegal is d16=0x4afc unimpl # jump addresses derived from effective address calculation -addrpc16: reloc is d16 [ reloc = inst_start+2+d16; ] { export *[ram]:4 reloc; } -addrd16: d16 is d16 { export *[ram]:4 d16; } -addrd32: d32 is d32 { export *[ram]:4 d32; } - -:jmp (regan) is opbig=0x4e & op67=3 & mode=2 & regan { goto [regan]; } -:jmp (d16,regan) is opbig=0x4e & op67=3 & mode=5 & regan; d16 { local tmp = regan + d16; goto [tmp]; } -:jmp (extw) is opbig=0x4e & op67=3 & mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; goto [extw]; } +addrpc16: reloc is d16 [ reloc = inst_start+2+d16; ] { export *[ram]:4 reloc; } +addrd16: d16".w" is d16 { export *[ram]:4 d16; } +addrd32: d32".l" is d32 { export *[ram]:4 d32; } +addrReg: (regan) is regan { export regan; } +addrRegD16: (d16,regan) is regan; d16 {local tmp = regan + d16; export *[ram]:4 tmp; } +addrextw: (extw) is extw { export extw; } + +:jmp addrReg is opbig=0x4e & op67=3 & mode=2 & addrReg { goto [addrReg]; } +:jmp addrRegD16 is (opbig=0x4e & op67=3 & mode=5) ... & addrRegD16 { goto [addrRegD16]; } +:jmp addrextw is opbig=0x4e & op67=3 & mode=6 & regan; addrextw [ pcmode=0; regtfan=regan; ] { goto [addrextw]; } :jmp addrpc16 is opbig=0x4e & op67=3 & mode=7 & regan=2; addrpc16 { goto addrpc16; } -:jmp (extw) is opbig=0x4e & op67=3 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; goto [extw]; } -:jmp addrd16".w" is opbig=0x4e & op67=3 & mode=7 & regan=0; addrd16 { goto addrd16; } -:jmp addrd32".l" is opbig=0x4e & op67=3 & mode=7 & regan=1; addrd32 { goto addrd32; } +:jmp addrextw is opbig=0x4e & op67=3 & mode=7 & regan=3; addrextw [ pcmode=1; ] { goto [addrextw]; } +:jmp addrd16 is opbig=0x4e & op67=3 & mode=7 & regan=0; addrd16 { goto addrd16; } +:jmp addrd32 is opbig=0x4e & op67=3 & mode=7 & regan=1; addrd32 { goto addrd32; } -:jsr (regan) is opbig=0x4e & op67=2 & mode=2 & regan { SP=SP-4; *:4 SP = inst_next; call [regan]; } -:jsr (d16,regan) is opbig=0x4e & op67=2 & mode=5 & regan; d16 { SP=SP-4; *:4 SP = inst_next; local tmp = regan + d16; call [tmp]; } -:jsr (extw) is opbig=0x4e & op67=2 & mode=6 & regan; extw [ pcmode=0; regtfan=regan;] { build extw; SP=SP-4; *:4 SP=inst_next; call [extw];} +:jsr addrReg is opbig=0x4e & op67=2 & mode=2 & addrReg { SP=SP-4; *:4 SP = inst_next; call [addrReg]; } +:jsr addrRegD16 is (opbig=0x4e & op67=2 & mode=5) ... & addrRegD16 { SP=SP-4; *:4 SP = inst_next; call [addrRegD16]; } +:jsr addrextw is opbig=0x4e & op67=2 & mode=6 & regan; addrextw [ pcmode=0; regtfan=regan;] { build addrextw; SP=SP-4; *:4 SP=inst_next; call [addrextw];} :jsr addrpc16 is opbig=0x4e & op67=2 & mode=7 & regan=2; addrpc16 { SP=SP-4; *:4 SP = inst_next; call addrpc16; } -:jsr (extw) is opbig=0x4e & op67=2 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; SP=SP-4; *:4 SP = inst_next; call [extw]; } -:jsr addrd16".w" is opbig=0x4e & op67=2 & mode=7 & regan=0; addrd16 { SP=SP-4; *:4 SP = inst_next; call addrd16; } -:jsr addrd32".l" is opbig=0x4e & op67=2 & mode=7 & regan=1; addrd32 { SP=SP-4; *:4 SP = inst_next; call addrd32; } +:jsr addrextw is opbig=0x4e & op67=2 & mode=7 & regan=3; addrextw [ pcmode=1; ] { build addrextw; SP=SP-4; *:4 SP = inst_next; call [addrextw]; } +:jsr addrd16 is opbig=0x4e & op67=2 & mode=7 & regan=0; addrd16 { SP=SP-4; *:4 SP = inst_next; call addrd16; } +:jsr addrd32 is opbig=0x4e & op67=2 & mode=7 & regan=1; addrd32 { SP=SP-4; *:4 SP = inst_next; call addrd32; } :lea eaptr,reg9an is (op=4 & reg9an & op68=7)... & eaptr { reg9an = eaptr; } @@ -1570,10 +1588,10 @@ macro shiftCXFlags(cntreg) { XF = CF * (cntreg != 0) + XF * (cntreg == 0); } -:lsl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=1 & regdnb { logicalShiftLeft(cntreg, regdnb, 8); } -:lsl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=1 & regdnw { logicalShiftLeft(cntreg, regdnw, 16); } -:lsl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=1 & regdn { logicalShiftLeft(cntreg, regdn, 32); } -:lsl eaw is (opbig=0xe3 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { +:lsl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=1 & regdnb { logicalShiftLeft(cntreg, regdnb, 8); } +:lsl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=1 & regdnw { logicalShiftLeft(cntreg, regdnw, 16); } +:lsl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=1 & regdn { logicalShiftLeft(cntreg, regdn, 32); } +:lsl eaw is (opbig=0xe3 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { local value:2 = eaw; getbit(CF, value, 15); value = value << 1; @@ -1583,10 +1601,10 @@ macro shiftCXFlags(cntreg) { XF = CF; } -:lsr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=1 & regdnb { logicalShiftRight(cntreg, regdnb, 8); } -:lsr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=1 & regdnw { logicalShiftRight(cntreg, regdnw, 16); } -:lsr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=1 & regdn { logicalShiftRight(cntreg, regdn, 32); } -:lsr eaw is (opbig=0xe2 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { +:lsr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=1 & regdnb { logicalShiftRight(cntreg, regdnb, 8); } +:lsr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=1 & regdnw { logicalShiftRight(cntreg, regdnw, 16); } +:lsr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=1 & regdn { logicalShiftRight(cntreg, regdn, 32); } +:lsr eaw is (opbig=0xe2 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { local value:2 = eaw; getbit(CF, value, 0); value = value >> 1; @@ -1615,35 +1633,65 @@ macro shiftCXFlags(cntreg) { @ifdef MC68040 -:move16 (regan)+,(regxan)+ is opbig=0xf6 & op37=4 & regan; regxan & da=1 {local src=regan&0xfffffff0; local dst=regxan&0xfffffff0; regan=regan+16; regxan=regxan+16; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } -:move16 (regan)+,(d32)".l" is opbig=0xf6 & op37=0 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0; regan=regan+16; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } -:move16 (d32)".l",(regan)+ is opbig=0xf6 & op37=1 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0; regan=regan+16; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } -:move16 (regan),(d32)".l" is opbig=0xf6 & op37=2 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } -:move16 (d32)".l",(regan) is opbig=0xf6 & op37=3 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; - *:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } +macro move16(src, dst) +{ + *:4 dst= *:4 src; + src=src+4; + dst=dst+4; + *:4 dst= *:4 src; + src=src+4; + dst=dst+4; + *:4 dst= *:4 src; + src=src+4; + dst=dst+4; + *:4 dst= *:4 src; +} + +:move16 regPlus,regxPlus is opbig=0xf6 & op37=4 & regan & regPlus; regxan & regxPlus & da=1 { + local src=regan&0xfffffff0; + local dst=regxan&0xfffffff0; + regan=regan+16; + regxan=regxan+16; + move16(src, dst); +} +:move16 regPlus,d32l is opbig=0xf6 & op37=0 & regan & regPlus; d32 & d32l { + local src=regan&0xfffffff0; + local dst:4=d32&0xfffffff0; + regan=regan+16; + move16(src, dst); +} + +:move16 d32l,regPlus is opbig=0xf6 & op37=1 & regan & regPlus; d32 & d32l { + local dst=regan&0xfffffff0; + local src:4=d32&0xfffffff0; + regan=regan+16; + move16(src, dst); +} +:move16 regParen,d32l is opbig=0xf6 & op37=2 & regan & regParen; d32 & d32l { + local src=regan&0xfffffff0; + local dst:4=d32&0xfffffff0; + move16(src, dst); +} +:move16 d32l,regParen is opbig=0xf6 & op37=3 & regan & regParen; d32 & d32l { + local dst=regan&0xfffffff0; + local src:4=d32&0xfffffff0; + move16(src, dst); +} @endif # MC68040 @ifdef COLDFIRE -:mvs.b: eab, reg9dn is (op=0x7 & op68=4 & reg9dn )... &eab { reg9dn = sext(eab); } -:mvs.w: eaw, reg9dn is (op=0x7 & op68=5 & reg9dn )... &eaw { reg9dn = sext(eaw); } -:mvz.b: eab, reg9dn is (op=0x7 & op68=6 & reg9dn )... &eab { reg9dn = zext(eab); } -:mvz.w: eaw, reg9dn is (op=0x7 & op68=7 & reg9dn )... &eaw { reg9dn = zext(eaw); } -:mov3q "#"^d911, eal is (op=0xa & op68=5 & d911 ) ... &eal { eal = d911; } +:mvs.b: eab, reg9dn is (op=0x7 & op68=4 & reg9dn )... & eab { reg9dn = sext(eab); } +:mvs.w: eaw, reg9dn is (op=0x7 & op68=5 & reg9dn )... & eaw { reg9dn = sext(eaw); } +:mvz.b: eab, reg9dn is (op=0x7 & op68=6 & reg9dn )... & eab { reg9dn = zext(eab); } +:mvz.w: eaw, reg9dn is (op=0x7 & op68=7 & reg9dn )... & eaw { reg9dn = zext(eaw); } + +:mov3q "#"^d911, eal is (op=0xa & op68=5 & d911 ) ... & eal { eal = d911; } :sats.l regdn is opbig=0x4c & op37=0x10 & regdn { if (VF == 0) goto inst_next; regdn = (zext(regdn == 0 ) * 0x80000000) + (zext(regdn != 0) * 0x7fffffff); VF=0; CF=0; } -skip_addr: skipAddr is op02=2 [skipAddr = inst_next + 2;] { export *[ram]:4 skipAddr; } -skip_addr: skipAddr is op02=3 [skipAddr = inst_next + 4;] { export *[ram]:4 skipAddr; } +skip_addr: skipAddr is op02=2 [skipAddr = inst_next + 2;] { export *[ram]:4 skipAddr; } +skip_addr: skipAddr is op02=3 [skipAddr = inst_next + 4;] { export *[ram]:4 skipAddr; } # TPF.w/l is occassionally used as a branch over a valid instruction. :tpf is opbig=0x51 & op37=0x1f & op02=4 { } # nop @@ -1863,44 +1911,36 @@ m2rfl0: { m2rfl1" "SP} is SP & mvm15=1 & m2rfl1 { SP = *movemptr; movemptr = mov m2rfl0: { m2rfl1} is mvm15=0 & m2rfl1 { } +movemOp: (regan) is mode=2 & regan { export regan; } +movemOp: (regan)+ is mode=3 & regan { export regan; } +movemOp: -(regan) is mode=4 & regan { export regan; } +movemOp: (d16, regan) is mode=5 & regan; fldpar ; d16 { local tmp = regan + d16; export tmp; } +movemOp: (extw) is mode=6 & regan; fldpar ; extw [ pcmode=0; regtfan=regan; ] {build extw; export extw; } +movemOp: (d16)".w" is mode=7 & regan=0; fldpar; d16 { local tmp:4 = d16; export tmp; } +movemOp: (d32)".l" is mode=7 & regan=1; fldpar; d32 { local tmp:4 = d32; export tmp; } +movemOp: (d16,PC) is op10=1 & mode=7 & regan=2; fldpar; d16 & PC { local tmp = inst_start + 4 + d16:4; export tmp; } +movemOp: (extw) is op10=1 & mode=7 & regan=3; fldpar; extw [ pcmode=1; ] { build extw; export extw; } -:movem.w r2mfw0,(regan) is opbig=0x48 & op67=2 & mode=2 & regan; r2mfw0 { movemptr = regan; build r2mfw0; } -:movem.w r2mbw0,-(regan) is opbig=0x48 & op67=2 & mode=4 & regan; r2mbw0 { movemptr = regan; build r2mbw0; regan = movemptr; } -:movem.w r2mfw0,(d16,regan) is opbig=0x48 & op67=2 & mode=5 & regan; r2mfw0; d16 { movemptr = regan+d16; build r2mfw0; } -:movem.w r2mfw0,(extw) is opbig=0x48 & op67=2 & mode=6 & regan; r2mfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfw0; } -:movem.w r2mfw0,(d16)".w" is opbig=0x48 & op67=2 & mode=7 & regan=0; r2mfw0; d16 { movemptr = d16; build r2mfw0; } -:movem.w r2mfw0,(d32)".l" is opbig=0x48 & op67=2 & mode=7 & regan=1; r2mfw0; d32 { movemptr = d32; build r2mfw0; } -:movem.l r2mfl0,(regan) is opbig=0x48 & op67=3 & mode=2 & regan; r2mfl0 { movemptr = regan; build r2mfl0; } -:movem.l r2mbl0,-(regan) is opbig=0x48 & op67=3 & mode=4 & regan; r2mbl0 { movemptr = regan; build r2mbl0; regan = movemptr; } -:movem.l r2mfl0,(d16,regan) is opbig=0x48 & op67=3 & mode=5 & regan; r2mfl0; d16 { movemptr = regan+d16; build r2mfl0; } -:movem.l r2mfl0,(extw) is opbig=0x48 & op67=3 & mode=6 & regan; r2mfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfl0; } -:movem.l r2mfl0,(d16)".w" is opbig=0x48 & op67=3 & mode=7 & regan=0; r2mfl0; d16 { movemptr = d16; build r2mfl0; } -:movem.l r2mfl0,(d32)".l" is opbig=0x48 & op67=3 & mode=7 & regan=1; r2mfl0; d32 { movemptr = d32; build r2mfl0; } - -:movem.w (regan),m2rfw0 is opbig=0x4c & op67=2 & mode=2 & regan; m2rfw0 { movemptr = regan; build m2rfw0; } -:movem.w (regan)+,m2rfw0 is opbig=0x4c & op67=2 & mode=3 & regan; m2rfw0 { movemptr = regan; build m2rfw0; regan = movemptr; } -:movem.w (d16,regan),m2rfw0 is opbig=0x4c & op67=2 & mode=5 & regan; m2rfw0; d16 { movemptr = regan+d16; build m2rfw0; } -:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=6 & regan; m2rfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfw0; } -:movem.w (d16,PC),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=2; m2rfw0; d16 & PC { movemptr = inst_start+4+d16; build m2rfw0; } -:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=3; m2rfw0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfw0; } -:movem.w (d16)".w",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=0; m2rfw0; d16 { movemptr = d16; build m2rfw0; } -:movem.w (d32)".l",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=1; m2rfw0; d32 { movemptr = d32; build m2rfw0; } -:movem.l (regan),m2rfl0 is opbig=0x4c & op67=3 & mode=2 & regan; m2rfl0 { movemptr = regan; build m2rfl0; } -:movem.l (regan)+,m2rfl0 is opbig=0x4c & op67=3 & mode=3 & regan; m2rfl0 { movemptr = regan; build m2rfl0; regan = movemptr; } -:movem.l (d16,regan),m2rfl0 is opbig=0x4c & op67=3 & mode=5 & regan; m2rfl0; d16 { movemptr = regan+d16; build m2rfl0; } -:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=6 & regan; m2rfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfl0; } -:movem.l (d16,PC),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=2; m2rfl0; d16 & PC { movemptr = inst_start+4+d16; build m2rfl0; } -:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=3; m2rfl0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfl0; } -:movem.l (d16)".w",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=0; m2rfl0; d16 { movemptr = d16; build m2rfl0; } -:movem.l (d32)".l",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=1; m2rfl0; d32 { movemptr = d32; build m2rfl0; } - -:movep.w (d16,regan),reg9dnw is op=0 & reg9dnw & op68=4 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; lo:1 = *:1(src+2); reg9dnw = (zext(ho) << 8) | zext(lo); } -:movep.l (d16,regan),reg9dn is op=0 & reg9dn & op68=5 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; mu:1 = *:1(src+2); ml:1 = *(src+4); lo:1 = *:1(src+6); reg9dn = (zext(ho) << 24) | (zext(mu) << 16) | (zext(ml) << 8) | zext(lo); } -:movep.w reg9dnw,(d16,regan) is op=0 & reg9dnw & op68=6 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dnw >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dnw:1; } -:movep.l reg9dn,(d16,regan) is op=0 & reg9dn & op68=7 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dn >> 24); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 16); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dn:1; } - - -:moveq "#"^d8base,reg9dn is op=7 & reg9dn & op8=0 & d8base { reg9dn = d8base; resflags(reg9dn); logflags(); } +movemWrt: is (mode=3 | mode=4) & regan { regan = movemptr; } +movemWrt: is mode { } + +:movem.w r2mfw0, movemOp is (opbig=0x48 & op67=2; r2mfw0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mfw0; } +:movem.w r2mbw0, movemOp is (opbig=0x48 & op67=2 & mode=4 & movemWrt; r2mbw0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mbw0; build movemWrt; } + +:movem.l r2mfl0, movemOp is (opbig=0x48 & op67=3; r2mfl0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mfl0; } +:movem.l r2mbl0, movemOp is (opbig=0x48 & op67=3 & mode=4 & movemWrt; r2mbl0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mbl0; build movemWrt; } + +:movem.w movemOp, m2rfw0 is (opbig=0x4c & op67=2 & movemWrt; m2rfw0) ... & movemOp { build movemOp; movemptr = movemOp; build m2rfw0; build movemWrt; } +:movem.l movemOp, m2rfl0 is (opbig=0x4c & op67=3 & movemWrt; m2rfl0) ... & movemOp { build movemOp; movemptr = movemOp; build m2rfl0; build movemWrt; } + + +epw: (d16, regan) is regan; d16 { local tmp = regan + d16; export tmp; } +:movep.w epw,reg9dnw is (op=0 & reg9dnw & op68=4 & op35=1) ... & epw { src:4 = epw; ho:1 = *:1 src; lo:1 = *:1(src+2); reg9dnw = (zext(ho) << 8) | zext(lo); } +:movep.l epw,reg9dn is (op=0 & reg9dn & op68=5 & op35=1) ... & epw { src:4 = epw; ho:1 = *:1 src; mu:1 = *:1(src+2); ml:1 = *(src+4); lo:1 = *:1(src+6); reg9dn = (zext(ho) << 24) | (zext(mu) << 16) | (zext(ml) << 8) | zext(lo); } +:movep.w reg9dnw,epw is (op=0 & reg9dnw & op68=6 & op35=1) ... & epw { src:4 = epw; local tmp = (reg9dnw >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dnw:1; } +:movep.l reg9dn,epw is (op=0 & reg9dn & op68=7 & op35=1)... & epw { src:4 = epw; local tmp = (reg9dn >> 24); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 16); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dn:1; } + +:moveq d8base,reg9dn is op=7 & reg9dn & op8=0 & d8base { reg9dn = d8base; resflags(reg9dn); logflags(); } :moves.b rreg,e2b is opbig=0x0e & op67=0 & mode & regan; rreg & wl=1; e2b [ regtsan=regan; savmod2=mode; ] { e2b = rreg:1; } :moves.w rreg,e2w is opbig=0x0e & op67=1 & mode & regan; rreg & wl=1; e2w [ regtsan=regan; savmod2=mode; ] { e2w = rreg:2; } @@ -1953,7 +1993,7 @@ submul: regdr-regdq is regdq & divsgn=0 & divsz=1 & regdr { } :mul^mulsize e2l,submul is opbig=0x4c & op67=0 & $(DAT_ALTER_ADDR_MODES); submul & mulsize; e2l [ savmod2=savmod1; regtsan=regtfan; ] { glbdenom=e2l; build submul; } -:nbcd eab is (opbig=0x48 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { +:nbcd eab is (opbig=0x48 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { local tmp = eab; CF = (tmp != 0) || (XF == 1); tmp = 0 - tmp - XF; @@ -1979,11 +2019,11 @@ macro negResFlags(result) { ZF = result == 0; } -:neg.b eab is (opbig=0x44 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab +:neg.b eab is (opbig=0x44 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { o2:1=eab; negFlags(o2); o2 = -o2; eab=o2; negResFlags(o2); } -:neg.w eaw is (opbig=0x44 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw +:neg.w eaw is (opbig=0x44 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { o2:2=eaw; negFlags(o2); o2 = -o2; eaw=o2; negResFlags(o2); } -:neg.l eal is (opbig=0x44 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal +:neg.l eal is (opbig=0x44 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { o2:4=eal; negFlags(o2); o2 = -o2; eal=o2; negResFlags(o2); } # NB: For the negx insn the CF and ZF flags are not set like other insns, from the manual: @@ -1993,11 +2033,11 @@ macro negResFlags(result) { # VF - Set if an overflow occurs; cleared otherwise. # CF - Set if borrow occurs; otherwise. -:negx.b eab is (opbig=0x40 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab +:negx.b eab is (opbig=0x40 & op67=0 & $(DAT_ALTER_ADDR_MODES))... & eab { local tmp = eab + XF; negxsubflags(tmp); tmp = -tmp; eab=tmp; extendedResultFlags(tmp); } -:negx.w eaw is (opbig=0x40 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw +:negx.w eaw is (opbig=0x40 & op67=1 & $(DAT_ALTER_ADDR_MODES))... & eaw { local tmp = eaw + zext(XF); negxsubflags(tmp); tmp = -tmp; eaw=tmp; extendedResultFlags(tmp); } -:negx.l eal is (opbig=0x40 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal +:negx.l eal is (opbig=0x40 & op67=2 & $(DAT_ALTER_ADDR_MODES))... & eal { local tmp = eal + zext(XF); negxsubflags(tmp); tmp = -tmp; eal=tmp; extendedResultFlags(tmp); } :nop is opbig=0x4e & op37=14 & op02=1 { } @@ -2035,20 +2075,20 @@ macro negResFlags(result) { @ifdef MC68040 -:pflushn "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=0 & regan unimpl -:pflush "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=1 & regan unimpl -:pflushan is opbig=0xf5 & op67=0 & op5=0 & op34=2 & regan=0 unimpl -:pflusha is opbig=0xf5 & op67=0 & op5=0 & op34=3 & regan=0 unimpl +:pflushn regPlus is opbig=0xf5 & op67=0 & op5=0 & op34=0 & regPlus unimpl +:pflush regPlus is opbig=0xf5 & op67=0 & op5=0 & op34=1 & regPlus unimpl +:pflushan is opbig=0xf5 & op67=0 & op5=0 & op34=2 & regan=0 unimpl +:pflusha is opbig=0xf5 & op67=0 & op5=0 & op34=3 & regan=0 unimpl @endif # MC68040 @ifdef MC68030 -:pflusha is opbig=0xf0 & op67=0 & mode=0 & regan=0; opx015=0x2400 unimpl +:pflusha is opbig=0xf0 & op67=0 & mode=0 & regan=0; opx015=0x2400 unimpl -FC: SFC is fc4=0 & fc3=0 & fc02=0 & SFC { export SFC; } -FC: DFC is fc4=0 & fc3=0 & fc02=1 & DFC { export DFC; } -FC: regdc is fc4=0 & fc3=1 & regdc { export regdc; } +FC: SFC is fc4=0 & fc3=0 & fc02=0 & SFC { export SFC; } +FC: DFC is fc4=0 & fc3=0 & fc02=1 & DFC { export DFC; } +FC: regdc is fc4=0 & fc3=1 & regdc { export regdc; } FC: "#"^fc03 is fc4=1 & fc3=0 & fc03 { export *[const]:4 fc03; } FCmask: "#"^fcmask is fcmask { export *[const]:1 fcmask; } @@ -2063,7 +2103,7 @@ FCmask: "#"^fcmask is fcmask { export *[const]:1 fcmask; } :pmove.l TC,e2l is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=1 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl :pmove.l e2l,TC is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=0 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl -:pmovefd.l e2l,TC is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl +:pmovefd.l e2l,TC is TC & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=0 & rwx=0 & fbit=1 & d8=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] unimpl :pmove.d SRP,e2d is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=1 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl :pmove.d e2d,SRP is SRP & opbig=0xf0 & op67=0 & $(CTL_ADDR_MODES); opx1315=2 & mregn=2 & rwx=0 & fbit=0 & d8=0; e2d [ savmod2=savmod1; regtsan=regtfan; ] unimpl @@ -2121,8 +2161,8 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; } @ifdef MC68040 -:ptestr "("^regan^")" is opbig=0xf5 & op67=1 & op35=5 & regan unimpl -:ptestw "("^regan^")" is opbig=0xf5 & op67=1 & op35=1 & regan unimpl +:ptestr regPlus is opbig=0xf5 & op67=1 & op35=5 & regPlus unimpl +:ptestw regPlus is opbig=0xf5 & op67=1 & op35=1 & regPlus unimpl @endif # MC68040 @@ -2130,12 +2170,12 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; } #TODO: PVALID - MC68851 only -:reset is d16=0x4e70 { reset(); } +:reset is d16=0x4e70 { reset(); } :rol.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=3 & regdnb { rotateLeft(cntreg, regdnb, 8); } :rol.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=3 & regdnw { rotateLeft(cntreg, regdnw, 16); } -:rol.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=3 & regdn { rotateLeft(cntreg, regdn, 32); } -:rol eaw is (opbig=0xe7 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { +:rol.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=3 & regdn { rotateLeft(cntreg, regdn, 32); } +:rol eaw is (opbig=0xe7 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { local value:2 = eaw; value = (value << 1) | (value >> 15); getbit(CF, value, 0); @@ -2146,8 +2186,8 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; } :ror.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=3 & regdnb { rotateRight(cntreg, regdnb, 8); } :ror.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=3 & regdnw { rotateRight(cntreg, regdnw, 16); } -:ror.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=3 & regdn { rotateRight(cntreg, regdn, 32); } -:ror eaw is (opbig=0xe6 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { +:ror.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=3 & regdn { rotateRight(cntreg, regdn, 32); } +:ror eaw is (opbig=0xe6 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { local value:2 = eaw; value = (value << 15) | (value >> 1); getbit(CF, value, 15); @@ -2159,7 +2199,7 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; } :roxl.b cntreg,regdnb is op=14 & cntreg & op8=1 & op67=0 & op34=2 & regdnb { rotateLeftExtended(cntreg, regdnb, 8); } :roxl.w cntreg,regdnw is op=14 & cntreg & op8=1 & op67=1 & op34=2 & regdnw { rotateLeftExtended(cntreg, regdnw, 16); } :roxl.l cntreg,regdn is op=14 & cntreg & op8=1 & op67=2 & op34=2 & regdn { rotateLeftExtended(cntreg, regdn, 32); } -:roxl eaw is (opbig=0xe5 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { +:roxl eaw is (opbig=0xe5 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { local value:2 = eaw; local xflag = (value & 0x8000) != 0; value = (value << 1) | zext(XF); @@ -2173,7 +2213,7 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; } :roxr.b cntreg,regdnb is op=14 & cntreg & op8=0 & op67=0 & op34=2 & regdnb { rotateRightExtended(cntreg, regdnb, 8); } :roxr.w cntreg,regdnw is op=14 & cntreg & op8=0 & op67=1 & op34=2 & regdnw { rotateRightExtended(cntreg, regdnw, 16); } :roxr.l cntreg,regdn is op=14 & cntreg & op8=0 & op67=2 & op34=2 & regdn { rotateRightExtended(cntreg, regdn, 32); } -:roxr eaw is (opbig=0xe4 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { +:roxr eaw is (opbig=0xe4 & op67=3 & $(MEM_ALTER_ADDR_MODES)) ... & eaw { local value:2 = eaw; local xflag = (value & 0x0001) != 0; value = (zext(XF) << 15) | (value >> 1); @@ -2195,7 +2235,7 @@ define pcodeop rtm; :rts is opbig=0x4e & op37=14 & op02=5 { PC = *SP; SP = SP+4; return [PC]; } -:sbcd Tyb,Txb is op=8 & op48=16 & Txb & Tyb { +:sbcd Tyb,Txb is op=8 & op48=16 & Txb & Tyb { CF = (Txb < Tyb) || ( (XF == 1) && (Txb == Tyb) ); Txb = Txb - Tyb - XF; Txb = bcdAdjust(Txb); @@ -2205,7 +2245,7 @@ define pcodeop rtm; :s^cc eab is (op=5 & cc & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { eab = -cc; } define pcodeop stop; -:stop const16 is opbig=0x4e & d8base=0x72; const16 { +:stop const16 is opbig=0x4e & d8base=0x72; const16 { SR = const16; unpackflags(SR); stop(); } @@ -2244,10 +2284,10 @@ define pcodeop stop; { tmp0:4 = zext(XF); subxflags(Tx, Ty); local tmp =tmp0+Ty; Tx=Tx-tmp; extendedResultFlags(Tx); } -:swap regdn is opbig=0x48 & op37=8 & regdn { logflags(); regdn = (regdn << 16) | (regdn>>16); resflags(regdn); } +:swap regdn is opbig=0x48 & op37=8 & regdn { logflags(); regdn = (regdn << 16) | (regdn>>16); resflags(regdn); } @ifndef COLDFIRE -:tas eab is (opbig=0x4a & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); resflags(eab); eab = eab | 0x80; } +:tas eab is (opbig=0x4a & op67=3 & $(DAT_ALTER_ADDR_MODES))... & eab { logflags(); resflags(eab); eab = eab | 0x80; } @endif # COLDFIRE :trap "#"^op03 is opbig=0x4e & op67=1 & op45=0 & op03 { vector:1 = op03; __m68k_trap(vector); } @@ -2256,21 +2296,21 @@ define pcodeop stop; :trap^cc^".l" const32 is op=5 & cc & op37=31 & op02=3; const32 { if (!cc) goto inst_next; SP = SP - 4; *:4 SP = inst_next; __m68k_trapv(); } :trapv is opbig=0x4e & op37=14 & op02=6 { if (!VF) goto inst_next; __m68k_trapv(); } -:tst.b eab is (opbig=0x4a & op67=0)... & eab { logflags(); resflags(eab); } -:tst.w eaw is (opbig=0x4a & op67=1)... & eaw { logflags(); resflags(eaw); } -:tst.l eal is (opbig=0x4a & op67=2)... & eal { logflags(); resflags(eal); } +:tst.b eab is (opbig=0x4a & op67=0)... & eab { logflags(); resflags(eab); } +:tst.w eaw is (opbig=0x4a & op67=1)... & eaw { logflags(); resflags(eaw); } +:tst.l eal is (opbig=0x4a & op67=2)... & eal { logflags(); resflags(eal); } @ifdef COLDFIRE -:tas eab is (opbig=0x4a & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eab { logflags(); resflags(eab); eab = eab | 0x80; } +:tas eab is (opbig=0x4a & op67=3 & $(MEM_ALTER_ADDR_MODES))... & eab { logflags(); resflags(eab); eab = eab | 0x80; } @endif # COLDFIRE -:unlk regan is opbig=0x4e & op37=11 & regan { SP = regan; regan = *SP; SP = SP+4; } +:unlk regan is opbig=0x4e & op37=11 & regan { SP = regan; regan = *SP; SP = SP+4; } -:unpk Tyw,Txw,const16 is op=8 & Txw & op48=24 & Tyw & rmbit=0; const16 { +:unpk Tyw,Txw,const16 is op=8 & Txw & op48=24 & Tyw & rmbit=0; const16 { Txw = (Txw & 0xF0F0) | ((((Tyw & 0x00F0) << 4) | (Tyw & 0x000F)) + const16); } -:unpk Tyb,Txw,const16 is op=8 & Tyb & op48=24 & Txw & rmbit=1; const16 { +:unpk Tyb,Txw,const16 is op=8 & Tyb & op48=24 & Txw & rmbit=1; const16 { local source:2 = zext(Tyb); source = (((source & 0x00F0) << 4) | (source & 0x000F)) + const16; Txw = (Txw & 0xF0F0) | source; @@ -2362,69 +2402,68 @@ f_mem: e2x is ffmt=2; e2x { tmp:10 = float2float(e2x); export tmp; } f_mem: e2x is ffmt=3; e2x { tmp:10 = float2float(e2x); export tmp; } f_mem: e2d is ffmt=5; e2d { tmp:10 = float2float(e2d); export tmp; } +:fabs.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x18) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = abs(f_mem); } -:fabs.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x18) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = abs(f_mem); } - -:fabs fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x18 { fdst = abs(fsrc); } +:fabs fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x18 { fdst = abs(fsrc); } @ifdef MC68040 -fabsrnd: "s" is fdst & fopmode=0x58 { tmp:4 = float2float(fdst); fdst = float2float(tmp); } -fabsrnd: "d" is fdst & fopmode=0x5c { tmp:8 = float2float(fdst); fdst = float2float(tmp); } +fabsrnd: "s" is fdst & fopmode=0x58 { tmp:4 = float2float(fdst); fdst = float2float(tmp); } +fabsrnd: "d" is fdst & fopmode=0x5c { tmp:8 = float2float(fdst); fdst = float2float(tmp); } -:f^fabsrnd^"abs."^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & fprec & (fopmode=0x58 | fopmode=0x5c)) ... & f_mem +:f^fabsrnd^"abs."^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fabsrnd & fprec & (fopmode=0x58 | fopmode=0x5c)) ... & f_mem [ savmod2=savmod1; regtsan=regtfan; ] { fdst = abs(f_mem); build fabsrnd; } -:f^fabsrnd^"abs" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fabsrnd & (fopmode=0x58 | fopmode=0x5c) { fdst = abs(fsrc); build fabsrnd; } +:f^fabsrnd^"abs" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fabsrnd & (fopmode=0x58 | fopmode=0x5c) { fdst = abs(fsrc); build fabsrnd; } @endif # MC68040 :facos.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1c) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = acos(f_mem);} -:facos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1c { fdst = acos(fsrc); } + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = acos(f_mem);} +:facos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1c { fdst = acos(fsrc); } :fadd.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x22) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f+ f_mem; } -:fadd fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x22 { fdst = fdst f+ fsrc; } + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f+ f_mem; } +:fadd fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x22 { fdst = fdst f+ fsrc; } @ifdef MC68040 -faddrnd: "s" is fdst & fopmode=0x62 { tmp:4 = float2float(fdst); fdst = float2float(tmp); } -faddrnd: "d" is fdst & fopmode=0x66 { tmp:8 = float2float(fdst); fdst = float2float(tmp); } +faddrnd: "s" is fdst & fopmode=0x62 { tmp:4 = float2float(fdst); fdst = float2float(tmp); } +faddrnd: "d" is fdst & fopmode=0x66 { tmp:8 = float2float(fdst); fdst = float2float(tmp); } -:f^faddrnd^"add."^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & fprec & (fopmode=0x62 | fopmode=0x66)) ... & f_mem +:f^faddrnd^"add."^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & faddrnd & fprec & (fopmode=0x62 | fopmode=0x66)) ... & f_mem [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f+ f_mem; build faddrnd; } -:f^faddrnd^"add" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & faddrnd & (fopmode=0x62 | fopmode=0x66) { fdst = fdst f+ fsrc; build faddrnd; } +:f^faddrnd^"add" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & faddrnd & (fopmode=0x62 | fopmode=0x66) { fdst = fdst f+ fsrc; build faddrnd; } @endif # MC68040 -:fasin.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0c) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = asin(f_mem);} -:fasin fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0c { fdst = asin(fsrc);} +:fasin.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0c) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = asin(f_mem);} +:fasin fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0c { fdst = asin(fsrc);} -:fatan.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0a) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = atan(f_mem);} -:fatan fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0a { fdst = atan(fsrc);} +:fatan.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0a) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = atan(f_mem);} +:fatan fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0a { fdst = atan(fsrc);} -:fatanh.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0d) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = tanh(f_mem);} -:fatanh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0d { fdst = tanh(fsrc);} +:fatanh.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x0d) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = tanh(f_mem);} +:fatanh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x0d { fdst = tanh(fsrc);} -:fb^fcc^".w" addr16 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=0 & fcc; addr16 { if (fcc) goto addr16; } -:fb^fcc^".l" addr32 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=1 & fcc; addr32 { if (fcc) goto addr32; } +:fb^fcc^".w" addr16 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=0 & fcc; addr16 { if (fcc) goto addr16; } +:fb^fcc^".l" addr32 is fop=15 & $(FP_FCOP) & f0808=0 & f0707=1 & fsize=1 & fcc; addr32 { if (fcc) goto addr32; } -:fcmp.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x38) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { local result = fdst f- f_mem; resflags_fp(result); } -:fcmp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x38 { local result=fdst f- fsrc; resflags_fp(result); } +:fcmp.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x38) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { local result = fdst f- f_mem; resflags_fp(result); } +:fcmp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x38 { local result=fdst f- fsrc; resflags_fp(result); } -:fcos.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1d) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = cos(f_mem);} -:fcos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1d { fdst = cos(fsrc);} +:fcos.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1d) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = cos(f_mem);} +:fcos fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1d { fdst = cos(fsrc);} -:fcosh.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x19) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = cosh(f_mem);} -:fcosh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x19 { fdst = cos(fsrc);} +:fcosh.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x19) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = cosh(f_mem);} +:fcosh fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x19 { fdst = cos(fsrc);} :fdb^fcc fcnt, addr16 is fop=15 & $(FP_FCOP) & f0308=9 & fcnt; f0615=0 & fcc; addr16 { if (fcc) goto inst_next; @@ -2434,7 +2473,7 @@ faddrnd: "d" is fdst & fopmode=0x66 { tmp:8 = float2float(fdst); fdst = float2f } :fdiv.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x20) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f/ f_mem;} + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f/ f_mem;} :fdiv fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x20 { fdst = fdst f/ fsrc;} @ifdef MC68040 @@ -2443,62 +2482,61 @@ fdivrnd: "s" is fdst & fopmode=0x60 { tmp:4 = float2float(fdst); fdst = float2f fdivrnd: "d" is fdst & fopmode=0x64 { tmp:8 = float2float(fdst); fdst = float2float(tmp); } :f^fdivrnd^"div."^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fdivrnd & fprec & (fopmode=0x60 | fopmode=0x64)) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f/ f_mem; build fdivrnd; } -:f^fdivrnd^"div" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fdivrnd & (fopmode=0x60 | fopmode=0x64) { fdst = fdst f/ fsrc; build fdivrnd; } + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fdst f/ f_mem; build fdivrnd; } +:f^fdivrnd^"div" fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fdivrnd & (fopmode=0x60 | fopmode=0x64) { fdst = fdst f/ fsrc; build fdivrnd; } @endif # MC68040 -:fetox.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec& fopmode=0x10) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fetox(f_mem); } -:fetox fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x10 { fdst = fetox(fsrc); } +:fetox.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec& fopmode=0x10) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fetox(f_mem); } +:fetox fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x10 { fdst = fetox(fsrc); } -:fetoxm1.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x08) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fetoxm1(f_mem); } -:fetoxm1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x08 { fdst = fetoxm1(fsrc); } +:fetoxm1.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x08) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fetoxm1(f_mem); } +:fetoxm1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x08 { fdst = fetoxm1(fsrc); } -:fgetexp.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst &fprec & fopmode=0x1e) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fgetexp(f_mem); } -:fgetexp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1e { fdst = fgetexp(fsrc); } +:fgetexp.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst &fprec & fopmode=0x1e) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fgetexp(f_mem); } +:fgetexp fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1e { fdst = fgetexp(fsrc); } -:fgetman.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1f) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fgetman(f_mem); } -:fgetman fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1f { fdst = fgetman(fsrc); } +:fgetman.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x1f) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fgetman(f_mem); } +:fgetman fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x1f { fdst = fgetman(fsrc); } -:fint.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x01) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fint(f_mem, FPCR); } -:fint fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x01 { fdst = fint(fsrc); } +:fint.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x01) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fint(f_mem, FPCR); } +:fint fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x01 { fdst = fint(fsrc); } -:fintrz.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x03) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(f_mem); fdst = int2float(tmp); } -:fintrz fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x03 { tmp:8 = trunc(fsrc); fdst = int2float(tmp); } +:fintrz.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x03) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { tmp:8 = trunc(f_mem); fdst = int2float(tmp); } +:fintrz fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x03 { tmp:8 = trunc(fsrc); fdst = int2float(tmp); } -:flog10.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x15) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flog10(f_mem); } -:flog10 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x15 { fdst = flog10(fsrc); } +:flog10.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x15) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flog10(f_mem); } +:flog10 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x15 { fdst = flog10(fsrc); } -:flog2.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x16) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flog2(f_mem); } -:flog2 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x16 { fdst = flog2(fsrc); } +:flog2.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x16) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flog2(f_mem); } +:flog2 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x16 { fdst = flog2(fsrc); } -:flogn.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x14) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flogn(f_mem); } -:flogn fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x14 { fdst = flogn(fsrc); } +:flogn.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x14) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flogn(f_mem); } +:flogn fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x14 { fdst = flogn(fsrc); } -:flognp1.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x06) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flognp1(f_mem); } -:flognp1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x06 { fdst = flognp1(fsrc); } +:flognp1.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x06) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = flognp1(f_mem); } +:flognp1 fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x06 { fdst = flognp1(fsrc); } -:fmod.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0& fdst & fprec & fopmode=0x21) ... & f_mem +:fmod.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0& fdst & fprec & fopmode=0x21) ... & f_mem [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fmod(f_mem); } -:fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21 { fdst = fmod(fsrc); } - +:fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21 { fdst = fmod(fsrc); } -:fmove.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x00) ... & f_mem - [ savmod2=savmod1; regtsan=regtfan; ] { fdst = f_mem; resflags_fp(fdst); } +:fmove.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x00) ... & f_mem + [ savmod2=savmod1; regtsan=regtfan; ] { fdst = f_mem; resflags_fp(fdst); } -:fmove fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x00 - { fdst = fsrc; resflags_fp(fdst); } +:fmove fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x00 + { fdst = fsrc; resflags_fp(fdst); } @ifdef MC68040 @@ -2514,33 +2552,36 @@ fmovernd: "d" is fdst & fopmode=0x44 { tmp:8 = float2fl #TODO: Documented decoding (w/ coprocess id in bits 10-12) conflicts with ASL instruction and differs from Instruction Format Summary # Convert float in fdst to an int and then move to byte -:fmove.b fdst, e2b is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=6; e2b +:fmove.b fdst, e2b is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=6; e2b [ savmod2=savmod1; regtsan=regtfan; ] { e2b = trunc(fdst); } # Convert float in fdst to an int and then move to word 16-bits -:fmove.w fdst, e2w is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=4; e2w - [ savmod2=savmod1; regtsan=regtfan; ] { e2w = trunc(fdst); } +:fmove.w fdst, e2w is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=4; e2w + [ savmod2=savmod1; regtsan=regtfan; ] { e2w = trunc(fdst); } # Convert float in fdst to an int and then move to long 32-bits -:fmove.l fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=0; e2l - [ savmod2=savmod1; regtsan=regtfan; ] { e2l = trunc(fdst); } +:fmove.l fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=0; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { e2l = trunc(fdst); } # destination is single float (32-bits) -:fmove.s fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=1; e2l - [ savmod2=savmod1; regtsan=regtfan; ] { e2l = float2float(fdst); resflags_fp(e2l); } +:fmove.s fdst, e2l is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & ffmt=1; e2l + [ savmod2=savmod1; regtsan=regtfan; ] { e2l = float2float(fdst); resflags_fp(e2l); } -:fmove.^fprec fdst, e2x is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_X); e2x - [ savmod2=savmod1; regtsan=regtfan; ] { e2x = float2float(fdst); resflags_fp(e2x); } +:fmove.^fprec fdst, e2x is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_X); e2x + [ savmod2=savmod1; regtsan=regtfan; ] { e2x = float2float(fdst); resflags_fp(e2x); } # Double float (64-bits) -:fmove.^fprec fdst, e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_D); e2d - [ savmod2=savmod1; regtsan=regtfan; ] { e2d = float2float(fdst); resflags_fp(e2d); } +:fmove.^fprec fdst, e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_D); e2d + [ savmod2=savmod1; regtsan=regtfan; ] { e2d = float2float(fdst); resflags_fp(e2d); } -:fmove.p fdst, e2l {"#"fkfactor} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfactor & $(FPREC_P); e2l - [ savmod2=savmod1; regtsan=regtfan; ] { kfact:4 = fkfactor; e2l = kfactor(fdst, kfact); } +kfact: {"#"fkfactor} is fkfactor & $(FPREC_P) { local tmp:4 = fkfactor; export *[const]:4 tmp; } +kfact: {fkfacreg} is fkfacreg & $(FPREC_Pd) { export fkfacreg; } -:fmove.p fdst, e2l {fkfacreg} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_Pd); e2l - [ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, fkfacreg); } +:fmove.p fdst, e2l kfact is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & kfact & $(FPREC_P); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, kfact); } + +:fmove.p fdst, e2l kfact is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & kfact & $(FPREC_Pd); e2l + [ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, kfact); } #Special case for FMOVEM.L and must occur before it within this file :fmove.l e2l, FPCR is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=0 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPCR = e2l; } @@ -3019,6 +3060,7 @@ moveaccreg2: ACC3 is ACC3 & op01=3 { export ACC3; } accreg = accreg - tmp; accw = accw + tmp; } + :msaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ... { local tmp = reg03y * reg9an; diff --git a/pypcode/processors/8051/data/languages/80251.sinc b/pypcode/processors/8051/data/languages/80251.sinc index 64f7ee51..2658335a 100644 --- a/pypcode/processors/8051/data/languages/80251.sinc +++ b/pypcode/processors/8051/data/languages/80251.sinc @@ -225,7 +225,7 @@ macro pop24(val) { :ANL wrj47,wrj03 is $(GROUP3) & ophi=5 & oplo=13; wrj47 & wrj03 { wrj47 = wrj47 & wrj03; resultflags(wrj47); } # ANL Rm,#data -:ADD rm47,Data is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 & Data; resultflags(rm47); } +:ANL rm47,Data is $(GROUP3) & ophi=5 & oplo=14; rm47 & s03=0; Data { rm47 = rm47 & Data; resultflags(rm47); } # ANL WRj,#data16 :ANL wrj47,Data16 is $(GROUP3) & ophi=5 & oplo=14; wrj47 & s03=4; Data16 { wrj47 = wrj47 & Data16; resultflags(wrj47); } diff --git a/pypcode/processors/8051/data/languages/8051_main.sinc b/pypcode/processors/8051/data/languages/8051_main.sinc index d3d40e01..22700c13 100644 --- a/pypcode/processors/8051/data/languages/8051_main.sinc +++ b/pypcode/processors/8051/data/languages/8051_main.sinc @@ -672,7 +672,7 @@ Rel16: relAddr is rel16 [ relAddr=inst_next+rel16; ] { export *:1 relAdd :ANL Areg,rn is $(GROUP2) & ophi=5 & Areg & rnfill=1 & rn { ACC = ACC & rn; resultflags(ACC); } :ANL Areg,Direct is $(GROUP1) & ophi=5 & oplo=5 & Areg; Direct { ACC = ACC & Direct; resultflags(ACC); } :ANL Areg,Ri is $(GROUP2) & ophi=5 & Areg & rifill=3 & Ri { ACC = ACC & Ri; resultflags(ACC); } -:ANL Areg,Data is $(GROUP2) & ophi=5 & oplo=4 & Areg; Data { ACC = ACC & Data; resultflags(ACC); } +:ANL Areg,Data is $(GROUP1) & ophi=5 & oplo=4 & Areg; Data { ACC = ACC & Data; resultflags(ACC); } :ANL Direct,Areg is $(GROUP1) & ophi=5 & oplo=2 & Areg; Direct { tmp:1 = Direct & ACC; Direct = tmp; resultflags(tmp); } :ANL Direct,Data is $(GROUP1) & ophi=5 & oplo=3; Direct; Data { tmp:1 = Direct & Data; Direct = tmp; resultflags(tmp); } diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64_apple.cspec b/pypcode/processors/AARCH64/data/languages/AARCH64_apple.cspec new file mode 100644 index 00000000..2cc05f2b --- /dev/null +++ b/pypcode/processors/AARCH64/data/languages/AARCH64_apple.cspec @@ -0,0 +1,270 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc b/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc index 0e61b3b2..af8ccb22 100644 --- a/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc +++ b/pypcode/processors/AARCH64/data/languages/AARCH64neon.sinc @@ -7285,7 +7285,7 @@ is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=1 & b_21=0 & Rm_FPR64 & b_15=0 & R :fmadd Rd_FPR32, Rn_FPR32, Rm_FPR32, Ra_FPR32 is m=0 & b_3030=0 & s=0 & b_2428=0x1f & ftype=0 & b_21=0 & Rm_FPR32 & b_15=0 & Ra_FPR32 & Rn_FPR32 & Rd_FPR32 & Zd { - Rd_FPR32 = Rn_FPR32 f+ (Rm_FPR32 f* Ra_FPR32); #NEON_fmadd(Rn_FPR32, Rm_FPR32, Ra_FPR32); + Rd_FPR32 = Ra_FPR32 f+ (Rm_FPR32 f* Rn_FPR32); #NEON_fmadd(Rn_FPR32, Rm_FPR32, Ra_FPR32); } # C7.2.100 FMADD page C7-2246 line 131323 MATCH x1f000000/mask=xff208000 diff --git a/pypcode/processors/AARCH64/data/languages/AppleSilicon.ldefs b/pypcode/processors/AARCH64/data/languages/AppleSilicon.ldefs index 51fb914d..438a3f92 100644 --- a/pypcode/processors/AARCH64/data/languages/AppleSilicon.ldefs +++ b/pypcode/processors/AARCH64/data/languages/AppleSilicon.ldefs @@ -10,7 +10,7 @@ manualindexfile="../manuals/AARCH64.idx" id="AARCH64:LE:64:AppleSilicon"> AppleSilicon ARM v8.5-A LE instructions, LE data, AMX extensions - + diff --git a/pypcode/processors/ARM/data/languages/ARM.ldefs b/pypcode/processors/ARM/data/languages/ARM.ldefs index e914419a..fca51e9a 100644 --- a/pypcode/processors/ARM/data/languages/ARM.ldefs +++ b/pypcode/processors/ARM/data/languages/ARM.ldefs @@ -5,7 +5,7 @@ endian="little" size="32" variant="v8" - version="1.107" + version="1.108" slafile="ARM8_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -29,7 +29,7 @@ endian="little" size="32" variant="v8T" - version="1.107" + version="1.108" slafile="ARM8_le.sla" processorspec="ARMtTHUMB.pspec" manualindexfile="../manuals/ARM.idx" @@ -52,7 +52,7 @@ instructionEndian="little" size="32" variant="v8LEInstruction" - version="1.107" + version="1.108" slafile="ARM8_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -68,7 +68,7 @@ endian="big" size="32" variant="v8" - version="1.107" + version="1.108" slafile="ARM8_be.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -91,7 +91,7 @@ endian="big" size="32" variant="v8T" - version="1.107" + version="1.108" slafile="ARM8_be.sla" processorspec="ARMtTHUMB.pspec" manualindexfile="../manuals/ARM.idx" @@ -111,7 +111,7 @@ endian="little" size="32" variant="v7" - version="1.107" + version="1.108" slafile="ARM7_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -134,7 +134,7 @@ instructionEndian="little" size="32" variant="v7LEInstruction" - version="1.107" + version="1.108" slafile="ARM7_le.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -150,7 +150,7 @@ endian="big" size="32" variant="v7" - version="1.107" + version="1.108" slafile="ARM7_be.sla" processorspec="ARMt.pspec" manualindexfile="../manuals/ARM.idx" @@ -171,7 +171,7 @@ endian="little" size="32" variant="Cortex" - version="1.107" + version="1.108" slafile="ARM7_le.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -195,7 +195,7 @@ endian="big" size="32" variant="Cortex" - version="1.107" + version="1.108" slafile="ARM7_be.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -218,7 +218,7 @@ endian="little" size="32" variant="v8-m" - version="1.107" + version="1.108" slafile="ARM8m_le.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -236,7 +236,7 @@ endian="big" size="32" variant="v8-m" - version="1.107" + version="1.108" slafile="ARM8m_be.sla" processorspec="ARMCortex.pspec" manualindexfile="../manuals/ARM.idx" @@ -255,7 +255,7 @@ endian="little" size="32" variant="v6" - version="1.107" + version="1.108" slafile="ARM6_le.sla" processorspec="ARMt_v6.pspec" manualindexfile="../manuals/ARM.idx" @@ -278,7 +278,7 @@ endian="big" size="32" variant="v6" - version="1.107" + version="1.108" slafile="ARM6_be.sla" processorspec="ARMt_v6.pspec" manualindexfile="../manuals/ARM.idx" @@ -301,7 +301,7 @@ endian="little" size="32" variant="v5t" - version="1.107" + version="1.108" slafile="ARM5t_le.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -322,7 +322,7 @@ endian="big" size="32" variant="v5t" - version="1.107" + version="1.108" slafile="ARM5t_be.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -343,7 +343,7 @@ endian="little" size="32" variant="v5" - version="1.107" + version="1.108" slafile="ARM5_le.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -362,7 +362,7 @@ endian="big" size="32" variant="v5" - version="1.101" + version="1.108" slafile="ARM5_be.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -381,7 +381,7 @@ endian="little" size="32" variant="v4t" - version="1.107" + version="1.108" slafile="ARM4t_le.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -401,7 +401,7 @@ endian="big" size="32" variant="v4t" - version="1.107" + version="1.108" slafile="ARM4t_be.sla" processorspec="ARMt_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -421,7 +421,7 @@ endian="little" size="32" variant="v4" - version="1.107" + version="1.108" slafile="ARM4_le.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" @@ -444,7 +444,7 @@ endian="big" size="32" variant="v4" - version="1.107" + version="1.108" slafile="ARM4_be.sla" processorspec="ARM_v45.pspec" manualindexfile="../manuals/ARM.idx" diff --git a/pypcode/processors/ARM/data/languages/ARMinstructions.sinc b/pypcode/processors/ARM/data/languages/ARMinstructions.sinc index ddd0fa64..4eba7c1b 100644 --- a/pypcode/processors/ARM/data/languages/ARMinstructions.sinc +++ b/pypcode/processors/ARM/data/languages/ARMinstructions.sinc @@ -2565,7 +2565,7 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate @if defined(VERSION_6) # cpy is a pre-UAL synonym for mov -:cpy^COND pc,rm is $(AMODE) & ARMcond=1 & COND & pc & c2027=0x1a & c1619=0 & c0411=0 & Rd=15 & rm +:cpy^COND pc,rm is $(AMODE) & ARMcond=1 & LRset=0 & COND & pc & c2027=0x1a & c1619=0 & c0411=0 & Rd=15 & rm { build COND; build rm; @@ -2573,6 +2573,22 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate goto [pc]; } +:cpy^COND pc,lr is $(AMODE) & ARMcond=1 & LRset=0 & COND & pc & c2527=0 & S20=0 & c2124=13 & c1619=0 & Rd=15 & sftimm=0 & c0406=0 & Rm=14 & lr +{ + build COND; + dest:4 = lr; + ALUWritePC(dest); + return [pc]; +} + +:cpy^COND pc,rm is $(AMODE) & ARMcond=1 & LRset=1 & COND & pc & c2027=0x1a & c1619=0 & c0411=0 & Rd=15 & rm +{ + build COND; + build rm; + BXWritePC(rm); + call [pc]; +} + :cpy^COND lr,rm is $(AMODE) & ARMcond=1 & COND & c2027=0x1a & c1619=0 & c0411=0 & Rd=14 & lr & rm & Rm2=15 [ LRset=1; globalset(inst_next,LRset); ] { @@ -3573,14 +3589,6 @@ ArmPCRelImmed12: reloff is U23=0 & immed & rotate lr = rm; } -:mov^COND pc,lr is $(AMODE) & pc & ARMcond=1 & COND & c2527=0 & S20=0 & c2124=13 & c1619=0 & Rd=15 & sftimm=0 & c0406=0 & Rm=14 & lr -{ - build COND; - dest:4 = lr; - ALUWritePC(dest); - return [pc]; -} - @if defined(VERSION_6T2) :movw^COND Rd,"#"^val is $(AMODE) & ARMcond=1 & COND & c2027=0x30 & c1619 & Rd & c0011 [ val = (c1619 << 12) | c0011; ] { diff --git a/pypcode/processors/ARM/data/languages/ARMneon.sinc b/pypcode/processors/ARM/data/languages/ARMneon.sinc index 70d5fb9f..888c5b91 100644 --- a/pypcode/processors/ARM/data/languages/ARMneon.sinc +++ b/pypcode/processors/ARM/data/languages/ARMneon.sinc @@ -2912,22 +2912,22 @@ RnAligned2: "["^VRn^vld1Align2^"]" is VRn & vld1Align2 { export VRn; } # VLD1 (single element to all lanes) # -vld1RnReplicate: is Rn & c0607=0 +vld1RnReplicate: is ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & VRn { val:8 = 0; - replicate1to8(*:1 Rn, val); + replicate1to8(*:1 VRn, val); export val; } -vld1RnReplicate: is Rn & c0607=1 +vld1RnReplicate: is ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & VRn { val:8 = 0; - replicate2to8(*:2 Rn, val); + replicate2to8(*:2 VRn, val); export val; } -vld1RnReplicate: is Rn & c0607=2 +vld1RnReplicate: is ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & VRn { val:8 = 0; - replicate4to8(*:4 Rn, val); + replicate4to8(*:4 VRn, val); export val; } @@ -2944,87 +2944,46 @@ buildVld1DdList3: vld1Dd3,buildVld1DdList3 is vld1Dd3 & buildVld1DdList3 [ coun build buildVld1DdList3; } -vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=0 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } -vld1DdList3: "{"^buildVld1DdList3^"}" is c0505=1 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } +vld1DdList3: "{"^buildVld1DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=1; ] { export 1:4; } +vld1DdList3: "{"^buildVld1DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld1DdList3 [ regNum=(D22<<4)+c1215-1; counter=2; ] { export 2:4; } +vld1DdList3: "{"^buildVld1DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } +vld1DdList3: "{"^buildVld1DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } -vld1Align3: is c0404=0 { } -vld1Align3: ":16" is c0404=1 & c0607=1 { } -vld1Align3: ":32" is c0404=1 & c0607=2 { } +vld1Align3: is TMode=0 & c0404=0 { } +vld1Align3: ":16" is TMode=0 & c0404=1 & c0607=1 { } +vld1Align3: ":32" is TMode=0 & c0404=1 & c0607=2 { } +vld1Align3: is TMode=1 & thv_c0404=0 { } +vld1Align3: ":16" is TMode=1 & thv_c0404=1 & thv_c0607=1 { } +vld1Align3: ":32" is TMode=1 & thv_c0404=1 & thv_c0607=2 { } -RnAligned3: "["^Rn^vld1Align3^"]" is Rn & vld1Align3 { export Rn; } +RnAligned3: "["^VRn^vld1Align3^"]" is VRn & vld1Align3 { export VRn; } @define vld1Constrain "((c0607=0 & c0404=0) | c0607=1 | c0607=2)" +@define T_vld1Constrain "((thv_c0607=0 & thv_c0404=0) | thv_c0607=1 | thv_c0607=2)" -:vld1.^esize0607 vld1DdList3,RnAligned3 is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & RnAligned3 & vld1RnReplicate & vld1DdList3 & c0811=12 & esize0607 & c0003=15 & $(vld1Constrain) +:vld1.^esize0607 vld1DdList3,RnAligned3 is ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=12 & c0003=15 & $(vld1Constrain)) | + ($(TMODE_F) & thv_c2327=19 & thv_c2021=2 & thv_c0811=12 & thv_c0003=15 & $(T_vld1Constrain)) & esize0607 & RnAligned3 & vld1RnReplicate & vld1DdList3 { mult_dat8 = vld1RnReplicate; build vld1DdList3; } -:vld1.^esize0607 vld1DdList3,RnAligned3^"!" is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & RnAligned3 & vld1RnReplicate & vld1DdList3 & c0811=12 & esize0607 & c0003=13 & $(vld1Constrain) +:vld1.^esize0607 vld1DdList3,RnAligned3^"!" is ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=12 & c0003=13 & $(vld1Constrain)) | + ($(TMODE_F) & thv_c2327=19 & thv_c2021=2 & thv_c0811=12 & thv_c0003=13 & $(T_vld1Constrain)) & esize0607 & RnAligned3 & vld1RnReplicate & vld1DdList3 { mult_dat8 = vld1RnReplicate; build vld1DdList3; - RnAligned3 = RnAligned3 + vld1DdList3; + RnAligned3 = RnAligned3 + esize0607; } -:vld1.^esize0607 vld1DdList3,RnAligned3,VRm is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & RnAligned3 & vld1RnReplicate & vld1DdList3 & c0811=12 & esize0607 & VRm & $(vld1Constrain) +:vld1.^esize0607 vld1DdList3,RnAligned3,VRm is ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=12 & $(vld1Constrain)) | + ($(TMODE_F) & thv_c2327=19 & thv_c2021=2 & thv_c0811=12 & $(T_vld1Constrain)) & esize0607 & VRm & RnAligned3 & vld1RnReplicate & vld1DdList3 { mult_dat8 = vld1RnReplicate; build vld1DdList3; RnAligned3 = RnAligned3 + VRm; } -thv_vld1RnReplicate: is VRn & thv_c0607=0 -{ - val:8 = 0; - replicate1to8(*:1 VRn, val); - export val; -} -thv_vld1RnReplicate: is VRn & thv_c0607=1 -{ - val:8 = 0; - replicate2to8(*:2 VRn, val); - export val; -} -thv_vld1RnReplicate: is VRn & thv_c0607=2 -{ - val:8 = 0; - replicate4to8(*:4 VRn, val); - export val; -} - -thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=0 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=1; ] { export 1:4; } -thv_vld1DdList3: "{"^buildVld1DdList3^"}" is thv_c0505=1 & thv_D22 & thv_c1215 & buildVld1DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; counter=2; ] { export 2:4; } - -thv_vld1Align3: is thv_c0404=0 { } -thv_vld1Align3: ":16" is thv_c0404=1 & thv_c0607=1 { } -thv_vld1Align3: ":32" is thv_c0404=1 & thv_c0607=2 { } - -VRnAligned3: "["^VRn^thv_vld1Align3^"]" is VRn & thv_vld1Align3 { export VRn; } - -@define T_vld1Constrain "((thv_c0607=0 & thv_c0404=0) | thv_c0607=1 | thv_c0607=2)" - -:vld1.^esize0607 thv_vld1DdList3,VRnAligned3 is $(TMODE_F) &thv_c2327=19 & thv_c2021=2 & VRnAligned3 & thv_vld1RnReplicate & thv_vld1DdList3 & thv_c0811=12 & esize0607 & thv_c0003=15 & $(T_vld1Constrain) -{ - mult_dat8 = thv_vld1RnReplicate; - build thv_vld1DdList3; -} - -:vld1.^esize0607 thv_vld1DdList3,VRnAligned3^"!" is $(TMODE_F) &thv_c2327=19 & thv_c2021=2 & VRnAligned3 & thv_vld1RnReplicate & thv_vld1DdList3 & thv_c0811=12 & esize0607 & thv_c0003=13 & $(T_vld1Constrain) -{ - mult_dat8 = thv_vld1RnReplicate; - build thv_vld1DdList3; - VRnAligned3 = VRnAligned3 + thv_vld1DdList3; -} - -:vld1.^esize0607 thv_vld1DdList3,VRnAligned3,VRm is $(TMODE_F) &thv_c2327=19 & thv_c2021=2 & VRnAligned3 & thv_vld1RnReplicate & thv_vld1DdList3 & thv_c0811=12 & esize0607 & VRm & $(T_vld1Constrain) -{ - mult_dat8 = thv_vld1RnReplicate; - build thv_vld1DdList3; - VRnAligned3 = VRnAligned3 + VRm; -} - ####### # VLD2 (multiple 2-element structures) # @@ -3144,8 +3103,22 @@ vld2DdList: "{"^buildVld2DdListA^buildVld2DdListB^"}" is TMode=1 & thv_c0811=3 & vld2Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } vld2Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } -vld2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index +vld2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0)) { + ptr:4 = &Dreg + vld2Index; + *[register]:1 ptr = *:1 mult_addr; +} + +vld2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1)) +{ + ptr:4 = &Dreg + (vld2Index * 2); + *[register]:2 ptr = *:2 mult_addr; +} + +vld2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2)) +{ + ptr:4 = &Dreg + (vld2Index * 4); + *[register]:4 ptr = *:4 mult_addr; } vld2Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { } @@ -3160,8 +3133,16 @@ vld2Align2: ":64" is TMode=1 & thv_c1011=2 & thv_c0405=1 { } vld2RnAligned2: "["^VRn^vld2Align2^"]" is VRn & vld2Align2 { export VRn; } buildVld2DdList2: is counter=0 { } -buildVld2DdList2: vld2DdElement2 is counter=1 & vld2DdElement2 [ counter=0; regNum=regNum+regInc; ] { } -buildVld2DdList2: vld2DdElement2,buildVld2DdList2 is vld2DdElement2 & buildVld2DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } +buildVld2DdList2: vld2DdElement2 is counter=1 & vld2DdElement2 [ counter=0; regNum=regNum+regInc; ] +{ + build vld2DdElement2; +} +buildVld2DdList2: vld2DdElement2,buildVld2DdList2 is vld2DdElement2 & buildVld2DdList2 & esize1011 [ counter=counter-1; regNum=regNum+regInc; ] +{ + build vld2DdElement2; + mult_addr = mult_addr + esize1011; + build buildVld2DdList2; +} vld2DdList2: "{"^buildVld2DdList2^"}" is TMode=0 & D22 & c1215 & buildVld2DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single vld2DdList2: "{"^buildVld2DdList2^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVld2DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double @@ -3171,19 +3152,48 @@ vld2DdList2: "{"^buildVld2DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) :vld2.^esize1011 vld2DdList2,vld2RnAligned2 is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003=15 ) | ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003=15 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2 - unimpl +{ + mult_addr = vld2RnAligned2; + build vld2DdList2; +} :vld2.^esize1011 vld2DdList2,vld2RnAligned2^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003=13 ) | ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003=13 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2 - unimpl +{ + mult_addr = vld2RnAligned2; + build vld2DdList2; + vld2RnAligned2 = vld2RnAligned2 + (2 * esize1011); +} :vld2.^esize1011 vld2DdList2,vld2RnAligned2,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=1 & c0003 ) | ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=1 & thv_c0003 ) ) & esize1011 & VRm & vld2RnAligned2 & vld2DdList2 - unimpl +{ + mult_addr = vld2RnAligned2; + build vld2DdList2; + vld2RnAligned2 = vld2RnAligned2 + VRm; +} ####### # VLD2 (single 2-element structure to all lanes) # +vld234Replicate: is ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) +{ + val:8 = 0; + replicate1to8(*:1 mult_addr, val); + export val; +} +vld234Replicate: is ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) +{ + val:8 = 0; + replicate2to8(*:2 mult_addr, val); + export val; +} +vld234Replicate: is ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) +{ + val:8 = 0; + replicate4to8(*:4 mult_addr, val); + export val; +} vld2Align3: is TMode=0 & c0404=0 { } vld2Align3: ":16" is TMode=0 & c0404=1 & c0607=0 { } @@ -3196,26 +3206,45 @@ vld2Align3: ":64" is TMode=1 & thv_c0404=1 & thv_c0607=2 { } vld2RnAligned3: "["^VRn^vld2Align3^"]" is VRn & vld2Align3 { export VRn; } -buildVld2DdList3: is counter=0 { } -buildVld2DdList3: Dreg^"[]" is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } -buildVld2DdList3: Dreg^"[]",buildVld2DdList3 is Dreg & buildVld2DdList3 [ counter=counter-1; regNum=regNum+regInc; ] { } +buildVld234DdList3: is counter=0 { } +buildVld234DdList3: Dreg^"[]" is counter=1 & Dreg & vld234Replicate [ counter=0; regNum=regNum+regInc; ] +{ + Dreg = vld234Replicate; +} +buildVld234DdList3: Dreg^"[]",buildVld234DdList3 is Dreg & buildVld234DdList3 & vld234Replicate & esize0607 [ counter=counter-1; regNum=regNum+regInc; ] +{ + Dreg = vld234Replicate; + mult_addr = mult_addr + esize0607; + build buildVld234DdList3; +} -vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld2DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single -vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld2DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double -vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld2DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single -vld2DdList3: "{"^buildVld2DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld2DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double +vld2DdList3: "{"^buildVld234DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single +vld2DdList3: "{"^buildVld234DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double +vld2DdList3: "{"^buildVld234DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single +vld2DdList3: "{"^buildVld234DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double :vld2.^esize0607 vld2DdList3,vld2RnAligned3 is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003=15 ) | ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003=15 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3 - unimpl +{ + mult_addr = vld2RnAligned3; + build vld2DdList3; +} :vld2.^esize0607 vld2DdList3,vld2RnAligned3^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003=13 ) | ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003=13 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3 - unimpl +{ + mult_addr = vld2RnAligned3; + build vld2DdList3; + vld2RnAligned3 = vld2RnAligned3 + 2 * esize0607; +} :vld2.^esize0607 vld2DdList3,vld2RnAligned3,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=13 & c0607<3 & c0003) | ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=13 & thv_c0607<3 & thv_c0003 ) ) & esize0607 & VRm & vld2RnAligned3 & vld2DdList3 - unimpl +{ + mult_addr = vld2RnAligned3; + build vld2DdList3; + vld2RnAligned3 = vld2RnAligned3 + VRm; +} ####### # VLD3 (multiple 3-element structures) @@ -3228,8 +3257,91 @@ vld3Align: ":64" is TMode=1 & thv_c0404=1 { } vld3RnAligned: "["^VRn^vld3Align^"]" is VRn & vld3Align { export VRn; } -buildVld3DdList: is counter=0 { } -buildVld3DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +vld3Dd: Dreg is (($(AMODE) & c0607=0) | ($(TMODE_F) & thv_c0607=0)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); +@endif # ENDIAN = "big" + mult_dat8 = 8; + + *[register]:1 ptr1 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr2 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr3 = *:1 mult_addr; + mult_addr = mult_addr + 1; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + ptr3 = ptr3 + 1; + goto ; + +} +vld3Dd: Dreg is (($(AMODE) & c0607=1) | ($(TMODE_F) & thv_c0607=1)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); +@endif # ENDIAN = "big" + mult_dat8 = 4; + + *[register]:2 ptr1 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr2 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr3 = *:2 mult_addr; + mult_addr = mult_addr + 2; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + ptr3 = ptr3 + 2; + goto ; + +} +vld3Dd: Dreg is (($(AMODE) & c0607=2) | ($(TMODE_F) & thv_c0607=2)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); +@endif # ENDIAN = "big" + mult_dat8 = 2; + + *[register]:4 ptr1 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr2 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr3 = *:4 mult_addr; + mult_addr = mult_addr + 4; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + ptr3 = ptr3 + 4; + goto ; + +} + +# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start +buildVld3DdList: is counter=0 & vld3Dd [ regNum=regNum-3*regInc; ] +{ + build vld3Dd; +} +buildVld3DdList: Dreg^buildVld3DdList is counter=1 & Dreg & buildVld3DdList [ counter=0; regNum=regNum+regInc; ] { } buildVld3DdList: Dreg,buildVld3DdList is Dreg & buildVld3DdList [ counter=counter-1; regNum=regNum+regInc; ] { } vld3DdList: "{"^buildVld3DdList^"}" is TMode=0 & c0811=4 & D22 & c1215 & buildVld3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single @@ -3238,13 +3350,27 @@ vld3DdList: "{"^buildVld3DdList^"}" is TMode=1 & thv_c0811=4 & thv_D22 & thv_c12 vld3DdList: "{"^buildVld3DdList^"}" is TMode=1 & thv_c0811=5 & thv_D22 & thv_c1215 & buildVld3DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double :vld3.^esize0607 vld3DdList,vld3RnAligned is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 & c0003=15 ) | - ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=15) ) & vld3RnAligned & esize0607 & vld3DdList unimpl + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=15) ) & vld3RnAligned & esize0607 & vld3DdList +{ + mult_addr = vld3RnAligned; + build vld3DdList; +} :vld3.^esize0607 vld3DdList,vld3RnAligned^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 & c0003=13 ) | - ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=13) ) & vld3RnAligned & esize0607 & vld3DdList unimpl + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 & thv_c0003=13) ) & vld3RnAligned & esize0607 & vld3DdList +{ + mult_addr = vld3RnAligned; + build vld3DdList; + vld3RnAligned = vld3RnAligned + (8 * 3); +} :vld3.^esize0607 vld3DdList,vld3RnAligned,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & (c0811=4 | c0811=5) & c0607<3 & c0505=0 ) | - ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 ) ) & VRm & vld3RnAligned & esize0607 & vld3DdList unimpl + ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & (thv_c0811=4 | thv_c0811=5) & thv_c0607<3 & thv_c0505=0 ) ) & VRm & vld3RnAligned & esize0607 & vld3DdList +{ + mult_addr = vld3RnAligned; + build vld3DdList; + vld3RnAligned = vld3RnAligned + VRm; +} ####### # VLD3 (single 3-element structure to one lane) @@ -3253,15 +3379,37 @@ vld3DdList: "{"^buildVld3DdList^"}" is TMode=1 & thv_c0811=5 & thv_D22 & thv_c12 vld3Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } vld3Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } -vld3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index +vld3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0)) { + ptr:4 = &Dreg + vld3Index; + *[register]:1 ptr = *:1 mult_addr; +} + +vld3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1)) +{ + ptr:4 = &Dreg + (vld3Index * 2); + *[register]:2 ptr = *:2 mult_addr; +} + +vld3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2)) +{ + ptr:4 = &Dreg + (vld3Index * 4); + *[register]:4 ptr = *:4 mult_addr; } vld3Rn: "["^VRn^"]" is VRn { export VRn; } buildVld3DdList2: is counter=0 { } -buildVld3DdList2: vld3DdElement2 is counter=1 & vld3DdElement2 [ counter=0; regNum=regNum+regInc; ] { } -buildVld3DdList2: vld3DdElement2,buildVld3DdList2 is vld3DdElement2 & buildVld3DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } +buildVld3DdList2: vld3DdElement2 is counter=1 & vld3DdElement2 [ counter=0; regNum=regNum+regInc; ] +{ + build vld3DdElement2; +} +buildVld3DdList2: vld3DdElement2,buildVld3DdList2 is vld3DdElement2 & buildVld3DdList2 & esize1011 [ counter=counter-1; regNum=regNum+regInc; ] +{ + build vld3DdElement2; + mult_addr = mult_addr + esize1011; + build buildVld3DdList2; +} vld3DdList2: "{"^buildVld3DdList2^"}" is TMode=0 & D22 & c1215 & buildVld3DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single vld3DdList2: "{"^buildVld3DdList2^"}" is TMode=0 & ((c1011=1 & c0405=2) | (c1011=2 & c0406=4)) & D22 & c1215 & buildVld3DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double @@ -3270,35 +3418,60 @@ vld3DdList2: "{"^buildVld3DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0405=2) :vld3.^esize1011 vld3DdList2,vld3Rn is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2 & c0003=15) | - ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=15) ) & vld3Rn & esize1011 & vld3DdList2 unimpl + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=15) ) & vld3Rn & esize1011 & vld3DdList2 +{ + mult_addr = vld3Rn; + build vld3DdList2; +} :vld3.^esize1011 vld3DdList2,vld3Rn^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2 & c0003=13) | - ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=13) ) & vld3Rn & esize1011 & vld3DdList2 unimpl + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2 & thv_c0003=13) ) & vld3Rn & esize1011 & vld3DdList2 +{ + mult_addr = vld3Rn; + build vld3DdList2; + vld3Rn = vld3Rn + (3 * esize1011); +} + :vld3.^esize1011 vld3DdList2,vld3Rn,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c1011<3 & c0809=2) | - ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2) ) & VRm & vld3Rn & esize1011 & vld3DdList2 unimpl + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c1011<3 & thv_c0809=2) ) & VRm & vld3Rn & esize1011 & vld3DdList2 +{ + mult_addr = vld3Rn; + build vld3DdList2; + vld3Rn = vld3Rn + VRm; +} ####### # VLD3 (single 3-element structure to all lanes) # -buildVld3DdList3: is counter=0 { } -buildVld3DdList3: Dreg^"[]" is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } -buildVld3DdList3: Dreg^"[]",buildVld3DdList3 is Dreg & buildVld3DdList3 [ counter=counter-1; regNum=regNum+regInc; ] { } - -vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld3DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single -vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld3DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double -vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld3DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single -vld3DdList3: "{"^buildVld3DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld3DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double +vld3DdList3: "{"^buildVld234DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList3: "{"^buildVld234DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double +vld3DdList3: "{"^buildVld234DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single +vld3DdList3: "{"^buildVld234DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double :vld3.^esize0607 vld3DdList3,vld3Rn is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0 & c0003=15) | - ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=15) ) & vld3Rn & esize0607 & vld3DdList3 unimpl + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=15) ) & vld3Rn & esize0607 & vld3DdList3 +{ + mult_addr = vld3Rn; + build vld3DdList3; +} :vld3.^esize0607 vld3DdList3,vld3Rn^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0 & c0003=13) | - ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=13) ) & vld3Rn & esize0607 & vld3DdList3 unimpl + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0 & thv_c0003=13) ) & vld3Rn & esize0607 & vld3DdList3 +{ + mult_addr = vld3Rn; + build vld3DdList3; + vld3Rn = vld3Rn + 3 * esize0607; +} :vld3.^esize0607 vld3DdList3,vld3Rn,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=14 & c0607<3 & c0404=0) | - ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0) ) & VRm & vld3Rn & esize0607 & vld3DdList3 unimpl + ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=14 & thv_c0404=0) ) & VRm & vld3Rn & esize0607 & vld3DdList3 +{ + mult_addr = vld3Rn; + build vld3DdList3; + vld3Rn = vld3Rn + VRm; +} ####### @@ -3399,38 +3572,10 @@ vld4Align3: ":128" is TMode=1 & thv_c0404=1 & thv_c0607=3 { } vld4RnAligned3: "["^VRn^vld4Align3^"]" is VRn & vld4Align3 { export VRn; } -vld4DdElement3: is Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) -{ - data:1 = *:1 mult_addr; - replicate1to8(data, Dreg); -} - -vld4DdElement3: is Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) -{ - data:2 = *:2 mult_addr; - replicate2to8(data, Dreg); -} - -vld4DdElement3: is Dreg & ((TMode=0 & c0607>1) | (TMode=1 & thv_c0607>1)) -{ - data:4 = *:4 mult_addr; - replicate4to8(data, Dreg); -} - -buildVld4DdList3: is counter=0 { } -buildVld4DdList3: Dreg^"[]" is counter=1 & Dreg & vld4DdElement3 [ counter=0; regNum=regNum+regInc; ] { build vld4DdElement3; } -buildVld4DdList3: Dreg^"[]",buildVld4DdList3 is vld4DdElement3 & Dreg & buildVld4DdList3 & vld4size0607 [ counter=counter-1; regNum=regNum+regInc; ] -{ - build vld4DdElement3; - mult_addr = mult_addr + vld4size0607; - build buildVld4DdList3; -} - -vld4DdList3: "{"^buildVld4DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld4DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single -vld4DdList3: "{"^buildVld4DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld4DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double -vld4DdList3: "{"^buildVld4DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld4DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single -vld4DdList3: "{"^buildVld4DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld4DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double - +vld4DdList3: "{"^buildVld234DdList3^"}" is TMode=0 & c0505=0 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single +vld4DdList3: "{"^buildVld234DdList3^"}" is TMode=0 & c0505=1 & D22 & c1215 & buildVld234DdList3 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=4; ] { } # Double +vld4DdList3: "{"^buildVld234DdList3^"}" is TMode=1 & thv_c0505=0 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=4; ] { } # Single +vld4DdList3: "{"^buildVld234DdList3^"}" is TMode=1 & thv_c0505=1 & thv_D22 & thv_c1215 & buildVld234DdList3 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double :vld4.^vld4size0607 vld4DdList3,vld4RnAligned3 is ($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=2 & c0811=0xf & c0003=0xf) | ($(TMODE_F) & thv_c2327=0x13 & thv_c2021=2 & thv_c0811=0xf & thv_c0003=0xf) & vld4size0607 & vld4RnAligned3 & vld4DdList3 @@ -3470,8 +3615,106 @@ vld4Align: ":256" is TMode=1 & thv_c0405=3 { } vld4RnAligned: "["^VRn^vld4Align^"]" is VRn & vld4Align { export VRn; } -buildVld4DdList: is counter=0 { } -buildVld4DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +vld4Dd: Dreg is (($(AMODE) & c0607=0) | ($(TMODE_F) & thv_c0607=0)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); + ptr4:4 = &Dreg + (regInc * 24); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); + ptr4:4 = &Dreg - (regInc * 24); +@endif # ENDIAN = "big" + mult_dat8 = 8; + + *[register]:1 ptr1 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr2 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr3 = *:1 mult_addr; + mult_addr = mult_addr + 1; + *[register]:1 ptr4 = *:1 mult_addr; + mult_addr = mult_addr + 1; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + ptr3 = ptr3 + 1; + ptr4 = ptr4 + 1; + goto ; + +} +vld4Dd: Dreg is (($(AMODE) & c0607=1) | ($(TMODE_F) & thv_c0607=1)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); + ptr4:4 = &Dreg + (regInc * 24); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); + ptr4:4 = &Dreg - (regInc * 24); +@endif # ENDIAN = "big" + mult_dat8 = 4; + + *[register]:2 ptr1 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr2 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr3 = *:2 mult_addr; + mult_addr = mult_addr + 2; + *[register]:2 ptr4 = *:2 mult_addr; + mult_addr = mult_addr + 2; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + ptr3 = ptr3 + 2; + ptr4 = ptr4 + 2; + goto ; + +} +vld4Dd: Dreg is (($(AMODE) & c0607=2) | ($(TMODE_F) & thv_c0607=2)) & Dreg & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); + ptr4:4 = &Dreg + (regInc * 24); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); + ptr4:4 = &Dreg - (regInc * 24); +@endif # ENDIAN = "big" + mult_dat8 = 2; + + *[register]:4 ptr1 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr2 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr3 = *:4 mult_addr; + mult_addr = mult_addr + 4; + *[register]:4 ptr4 = *:4 mult_addr; + mult_addr = mult_addr + 4; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + ptr3 = ptr3 + 4; + ptr4 = ptr4 + 4; + goto ; + +} + +# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start +buildVld4DdList: is counter=0 & vld4Dd [ regNum=regNum-4*regInc; ] +{ + build vld4Dd; +} +buildVld4DdList: Dreg^buildVld4DdList is counter=1 & Dreg & buildVld4DdList [ counter=0; regNum=regNum+regInc; ] { } buildVld4DdList: Dreg,buildVld4DdList is Dreg & buildVld4DdList [ counter=counter-1; regNum=regNum+regInc; ] { } vld4DdList: "{"^buildVld4DdList^"}" is TMode=0 & c0808=0 & D22 & c1215 & buildVld4DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single @@ -3481,15 +3724,26 @@ vld4DdList: "{"^buildVld4DdList^"}" is TMode=1 & thv_c0808=1 & thv_D22 & thv_c12 :vld4.^esize0607 vld4DdList,vld4RnAligned is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3 & c0003=15 ) | ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 & thv_c0003=15 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList - unimpl +{ + mult_addr = vld4RnAligned; + build vld4DdList; +} :vld4.^esize0607 vld4DdList,vld4RnAligned^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3 & c0003=13 ) | ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 & thv_c0003=13 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList - unimpl +{ + mult_addr = vld4RnAligned; + build vld4DdList; + vld4RnAligned = vld4RnAligned + (8 * 4); +} :vld4.^esize0607 vld4DdList,vld4RnAligned,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=2 & c0911=0 & c0607<3) | ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=2 & thv_c0911=0 & thv_c0607<3 ) ) & esize0607 & VRm & vld4RnAligned & vld4DdList - unimpl +{ + mult_addr = vld4RnAligned; + build vld4DdList; + vld4RnAligned = vld4RnAligned + VRm; +} @endif # SIMD @@ -4562,7 +4816,7 @@ vmlDmA: Dm_4^"["^thv_M5^"]" is TMode=1 & thv_c2021=2 & Dm_4 & thv_M5 { tmp2:8 = Qm(8); tmp1 = ~ tmp1; tmp2 = ~ tmp2; - Qd = (zext(tmp1) << 8) | zext(tmp2); + Qd = (zext(tmp2) << 64) | zext(tmp1); } define pcodeop FloatVectorNeg; @@ -5475,86 +5729,51 @@ vst1DdList: "{"^buildVst1DdList^"}" is TMode = 1 & thv_c0811=2 & thv_D22 & thv_c # VST1 (single element to one lane) # -vst1Index: val is c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } +vst1Index: val is TMode=0 & c0507 & c1011 [ val = c0507 >> c1011; ] { tmp:4 = val; export tmp; } +vst1Index: val is TMode=1 & thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } -vst1DdElement2: Dd^"["^vst1Index^"]" is Dd & vst1Index & c1011=0 +vst1DdElement2: Dd^"["^vst1Index^"]" is ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0)) & Dd & vst1Index { ptr:4 = &Dd + vst1Index; *:1 mult_addr = *[register]:1 ptr; } -vst1DdElement2: Dd^"["^vst1Index^"]" is Dd & vst1Index & c1011=1 +vst1DdElement2: Dd^"["^vst1Index^"]" is ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1)) & Dd & vst1Index { ptr:4 = &Dd + (2 * vst1Index); *:2 mult_addr = *[register]:2 ptr; } -vst1DdElement2: Dd^"["^vst1Index^"]" is Dd & vst1Index & c1011=2 +vst1DdElement2: Dd^"["^vst1Index^"]" is ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2)) & Dd & vst1Index { ptr:4 = &Dd + (4 * vst1Index); *:4 mult_addr = *[register]:4 ptr; } -@define Vst1DdElement2 "((c1011=0 & c0404=0) | (c1011=1 & c0505=0) | (c1011=2 & (c0406=0 | c0406=3))) & vst1DdElement2" +@define Vst1DdElement2 "((c1011=0 & c0404=0) | (c1011=1 & c0505=0) | (c1011=2 & (c0406=0 | c0406=3)))" +@define T_Vst1DdElement2 "((thv_c1011=0 & thv_c0404=0) | (thv_c1011=1 & thv_c0505=0) | (thv_c1011=2 & (thv_c0406=0 | thv_c0406=3)))" -:vst1.^esize1011 vst1DdElement2,RnAligned2 is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & RnAligned2 & esize1011 & c0809=0 & c0003=15 & $(Vst1DdElement2) +:vst1.^esize1011 vst1DdElement2,RnAligned2 is (($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c0809=0 & c0003=15 & $(Vst1DdElement2)) | + ($(TMODE_F) & thv_c2327=19 & thv_c2021=0 & thv_c0809=0 & thv_c0003=15 & $(T_Vst1DdElement2))) & RnAligned2 & esize1011 & vst1DdElement2 { mult_addr = RnAligned2; build vst1DdElement2; } -:vst1.^esize1011 vst1DdElement2,RnAligned2^"!" is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & RnAligned2 & esize1011 & c0809=0 & c0003=13 & $(Vst1DdElement2) +:vst1.^esize1011 vst1DdElement2,RnAligned2^"!" is (($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c0809=0 & c0003=13 & $(Vst1DdElement2)) | + ($(TMODE_F) & thv_c2327=19 & thv_c2021=0 & thv_c0809=0 & thv_c0003=13 & $(T_Vst1DdElement2))) & RnAligned2 & esize1011 & vst1DdElement2 { mult_addr = RnAligned2; build vst1DdElement2; RnAligned2 = RnAligned2 + esize1011; } -:vst1.^esize1011 vst1DdElement2,RnAligned2,VRm is $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & RnAligned2 & esize1011 & c0809=0 & VRm & $(Vst1DdElement2) +:vst1.^esize1011 vst1DdElement2,RnAligned2,VRm is (($(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c0809=0 & $(Vst1DdElement2)) | + ($(TMODE_F) & thv_c2327=19 & thv_c2021=0 & thv_c0809=0 & $(T_Vst1DdElement2))) & VRm & RnAligned2 & esize1011 & vst1DdElement2 { mult_addr = RnAligned2; build vst1DdElement2; RnAligned2 = RnAligned2 + VRm; } -thv_vst1Index: val is thv_c0507 & thv_c1011 [ val = thv_c0507 >> thv_c1011; ] { tmp:4 = val; export tmp; } - -thv_vst1DdElement2: Dd^"["^thv_vst1Index^"]" is Dd & thv_vst1Index & thv_c1011=0 -{ - ptr:4 = &Dd + thv_vst1Index; - *:1 mult_addr = *[register]:1 ptr; -} -thv_vst1DdElement2: Dd^"["^thv_vst1Index^"]" is Dd & thv_vst1Index & thv_c1011=1 -{ - ptr:4 = &Dd + (2 * thv_vst1Index); - *:2 mult_addr = *[register]:2 ptr; -} -thv_vst1DdElement2: Dd^"["^thv_vst1Index^"]" is Dd & thv_vst1Index & thv_c1011=2 -{ - ptr:4 = &Dd + (4 * thv_vst1Index); - *:4 mult_addr = *[register]:4 ptr; -} - -@define T_Vst1DdElement2 "((thv_c1011=0 & thv_c0404=0) | (thv_c1011=1 & thv_c0505=0) | (thv_c1011=2 & (thv_c0406=0 | thv_c0406=3))) & thv_vst1DdElement2" - -:vst1.^esize1011 thv_vst1DdElement2,RnAligned2 is $(TMODE_F) &thv_c2327=19 & thv_c2021=0 & RnAligned2 & esize1011 & thv_c0809=0 & thv_c0003=15 & $(T_Vst1DdElement2) -{ - mult_addr = RnAligned2; - build thv_vst1DdElement2; -} - -:vst1.^esize1011 thv_vst1DdElement2,RnAligned2^"!" is $(TMODE_F) &thv_c2327=19 & thv_c2021=0 & RnAligned2 & esize1011 & thv_c0809=0 & thv_c0003=13 & $(T_Vst1DdElement2) -{ - mult_addr = RnAligned2; - build thv_vst1DdElement2; - RnAligned2 = RnAligned2 + esize1011; -} - -:vst1.^esize1011 thv_vst1DdElement2,RnAligned2,VRm is $(TMODE_F) &thv_c2327=19 & thv_c2021=0 & RnAligned2 & esize1011 & thv_c0809=0 & VRm & $(T_Vst1DdElement2) -{ - mult_addr = RnAligned2; - build thv_vst1DdElement2; - RnAligned2 = RnAligned2 + VRm; -} - ####### # VST2 @@ -5677,8 +5896,22 @@ vst2DdList: "{"^buildVst2DdListA^buildVst2DdListB^"}" is TMode=1 & thv_c0811=3 & # VST2 (single 2-element structure to one lane) # -vst2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index +vst2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0)) +{ + ptr:4 = &Dreg + vld2Index; + *:1 mult_addr = *[register]:1 ptr; +} + +vst2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1)) { + ptr:4 = &Dreg + (vld2Index * 2); + *:2 mult_addr = *[register]:2 ptr; +} + +vst2DdElement2: Dreg^"["^vld2Index^"]" is Dreg & vld2Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2)) +{ + ptr:4 = &Dreg + (vld2Index * 4); + *:4 mult_addr = *[register]:4 ptr; } vst2Align2: is TMode=0 & c0404=0 & (c1111=0 | c0505=0) { } @@ -5693,8 +5926,16 @@ vst2Align2: ":64" is TMode=1 & thv_c1011=2 & thv_c0405=1 { } vst2RnAligned2: "["^VRn^vst2Align2^"]" is VRn & vst2Align2 { export VRn; } buildVst2DdList2: is counter=0 { } -buildVst2DdList2: vst2DdElement2 is counter=1 & vst2DdElement2 [ counter=0; regNum=regNum+regInc; ] { } -buildVst2DdList2: vst2DdElement2,buildVst2DdList2 is vst2DdElement2 & buildVst2DdList2 [ counter=counter-1; regNum=regNum+regInc; ] { } +buildVst2DdList2: vst2DdElement2 is counter=1 & vst2DdElement2 [ counter=0; regNum=regNum+regInc; ] +{ + build vst2DdElement2; +} +buildVst2DdList2: vst2DdElement2,buildVst2DdList2 is vst2DdElement2 & buildVst2DdList2 & esize1011 [ counter=counter-1; regNum=regNum+regInc; ] +{ + build vst2DdElement2; + mult_addr = mult_addr + esize1011; + build buildVst2DdList2; +} vst2DdList2: "{"^buildVst2DdList2^"}" is TMode=0 & D22 & c1215 & buildVst2DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single vst2DdList2: "{"^buildVst2DdList2^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVst2DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double @@ -5703,15 +5944,26 @@ vst2DdList2: "{"^buildVst2DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) :vst2.^esize1011 vst2DdList2,vst2RnAligned2 is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 & c0003=15 ) | ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 & thv_c0003=15 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 - unimpl +{ + mult_addr = vst2RnAligned2; + build vst2DdList2; +} :vst2.^esize1011 vst2DdList2,vst2RnAligned2^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 & c0003=13 ) | ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 & thv_c0003=13 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 - unimpl +{ + mult_addr = vst2RnAligned2; + build vst2DdList2; + vst2RnAligned2 = vst2RnAligned2 + (2 * esize1011); +} :vst2.^esize1011 vst2DdList2,vst2RnAligned2,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=1 ) | ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=1 ) ) & vst2RnAligned2 & esize1011 & vst2DdList2 & VRm - unimpl +{ + mult_addr = vst2RnAligned2; + build vst2DdList2; + vst2RnAligned2 = vst2RnAligned2 + VRm; +} ####### @@ -5731,8 +5983,91 @@ vst3Align: ":64" is TMode=1 & thv_c0404=1 { } vst3RnAligned: "["^VRn^vst3Align^"]" is VRn & vst3Align { export VRn; } -buildvst3DdList: is counter=0 { } -buildvst3DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +vst3Dd: Dreg is Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); +@endif # ENDIAN = "big" + mult_dat8 = 8; + + *:1 mult_addr = *[register]:1 ptr1; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr2; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr3; + mult_addr = mult_addr + 1; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + ptr3 = ptr3 + 1; + goto ; + +} +vst3Dd: Dreg is Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); +@endif # ENDIAN = "big" + mult_dat8 = 4; + + *:2 mult_addr = *[register]:2 ptr1; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr2; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr3; + mult_addr = mult_addr + 2; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + ptr3 = ptr3 + 2; + goto ; + +} +vst3Dd: Dreg is Dreg & ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); +@endif # ENDIAN = "big" + mult_dat8 = 2; + + *:4 mult_addr = *[register]:4 ptr1; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr2; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr3; + mult_addr = mult_addr + 4; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + ptr3 = ptr3 + 4; + goto ; + +} + +# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start +buildvst3DdList: is counter=0 & vst3Dd [ regNum=regNum-3*regInc; ] +{ + build vst3Dd; +} +buildvst3DdList: Dreg^buildvst3DdList is counter=1 & Dreg & buildvst3DdList [ counter=0; regNum=regNum+regInc; ] { } buildvst3DdList: Dreg,buildvst3DdList is Dreg & buildvst3DdList [ counter=counter-1; regNum=regNum+regInc; ] { } vst3DdList: "{"^buildvst3DdList^"}" is TMode=0 & c0811=4 & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single @@ -5743,15 +6078,26 @@ vst3DdList: "{"^buildvst3DdList^"}" is TMode=1 & thv_c0811=5 & thv_D22 & thv_c12 :vst3.^esize0607 vst3DdList,vst3RnAligned is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=15 ) | ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0003=15 ) ) & vst3RnAligned & esize0607 & vst3DdList - unimpl +{ + mult_addr = vst3RnAligned; + build vst3DdList; +} :vst3.^esize0607 vst3DdList,vst3RnAligned^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0003=13 ) | ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0003=13 ) ) & vst3RnAligned & esize0607 & vst3DdList - unimpl +{ + mult_addr = vst3RnAligned; + build vst3DdList; + vst3RnAligned = vst3RnAligned + (8 * 3); +} :vst3.^esize0607 vst3DdList,vst3RnAligned,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0) | ( $(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 ) ) & vst3RnAligned & esize0607 & vst3DdList & VRm - unimpl +{ + mult_addr = vst3RnAligned; + build vst3DdList; + vst3RnAligned = vst3RnAligned + VRm; +} ####### @@ -5760,22 +6106,64 @@ vst3DdList: "{"^buildvst3DdList^"}" is TMode=1 & thv_c0811=5 & thv_D22 & thv_c12 vst3Rn: "["^VRn^"]" is VRn { export VRn; } -vst3DdList2: "{"^buildvst3DdList^"}" is TMode=0 & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=2; ] { } # Single -vst3DdList2: "{"^buildvst3DdList^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildvst3DdList [ regNum=(D22<<4)+c1215-2; regInc=2; counter=2; ] { } # Double -vst3DdList2: "{"^buildvst3DdList^"}" is TMode=1 & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=2; ] { } # Single -vst3DdList2: "{"^buildvst3DdList^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildvst3DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=2; ] { } # Double +vst3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index & ((TMode=0 & c1011=0) | (TMode=1 & thv_c1011=0)) +{ + ptr:4 = &Dreg + vld3Index; + *:1 mult_addr = *[register]:1 ptr; +} + +vst3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index & ((TMode=0 & c1011=1) | (TMode=1 & thv_c1011=1)) +{ + ptr:4 = &Dreg + (vld3Index * 2); + *:2 mult_addr = *[register]:2 ptr; +} + +vst3DdElement2: Dreg^"["^vld3Index^"]" is Dreg & vld3Index & ((TMode=0 & c1011=2) | (TMode=1 & thv_c1011=2)) +{ + ptr:4 = &Dreg + (vld3Index * 4); + *:4 mult_addr = *[register]:4 ptr; +} + + +buildVst3DdList2: is counter=0 { } +buildVst3DdList2: vst3DdElement2 is counter=1 & vst3DdElement2 [ counter=0; regNum=regNum+regInc; ] +{ + build vst3DdElement2; +} +buildVst3DdList2: vst3DdElement2,buildVst3DdList2 is vst3DdElement2 & buildVst3DdList2 & esize1011 [ counter=counter-1; regNum=regNum+regInc; ] +{ + build vst3DdElement2; + mult_addr = mult_addr + esize1011; + build buildVst3DdList2; +} + +vst3DdList2: "{"^buildVst3DdList2^"}" is TMode=0 & D22 & c1215 & buildVst3DdList2 [ regNum=(D22<<4)+c1215-1; regInc=1; counter=3; ] { } # Single +vst3DdList2: "{"^buildVst3DdList2^"}" is TMode=0 & ((c1011=1 & c0505=1) | (c1011=2 & c0606=1)) & D22 & c1215 & buildVst3DdList2 [ regNum=(D22<<4)+c1215-2; regInc=2; counter=3; ] { } # Double +vst3DdList2: "{"^buildVst3DdList2^"}" is TMode=1 & thv_D22 & thv_c1215 & buildVst3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-1; regInc=1; counter=3; ] { } # Single +vst3DdList2: "{"^buildVst3DdList2^"}" is TMode=1 & ((thv_c1011=1 & thv_c0505=1) | (thv_c1011=2 & thv_c0606=1)) & thv_D22 & thv_c1215 & buildVst3DdList2 [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=3; ] { } # Double :vst3.^esize1011 vst3DdList2,vst3Rn is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 & c0003=15 ) | ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 & thv_c0003=15 ) ) & vst3Rn & esize1011 & vst3DdList2 - unimpl +{ + mult_addr = vst3Rn; + build vst3DdList2; +} :vst3.^esize1011 vst3DdList2,vst3Rn^"!" is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 & c0003=13 ) | ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 & thv_c0003=13 ) ) & vst3Rn & esize1011 & vst3DdList2 - unimpl +{ + mult_addr = vst3Rn; + build vst3DdList2; + vst3Rn = vst3Rn + (3 * esize1011); +} :vst3.^esize1011 vst3DdList2,vst3Rn,VRm is ( ( $(AMODE) & ARMcond=0 & cond=15 & c2327=9 & c2021=0 & c1011<3 & c0809=2 ) | ( $(TMODE_F) & thv_c2327=0x13 & thv_c2021=0 & thv_c1011<3 & thv_c0809=2 ) ) & vst3Rn & esize1011 & vst3DdList2 & VRm - unimpl +{ + mult_addr = vst3Rn; + build vst3DdList2; + vst3Rn = vst3Rn + VRm; +} ####### # VST4 (multiple 4-element structures) @@ -5792,8 +6180,106 @@ vst4Align: ":256" is TMode=1 & thv_c0405=3 { } vst4RnAligned: "["^VRn^vst4Align^"]" is VRn & vst4Align { export VRn; } -buildVst4DdList: is counter=0 { } -buildVst4DdList: Dreg is counter=1 & Dreg [ counter=0; regNum=regNum+regInc; ] { } +vst4Dd: Dreg is Dreg & ((TMode=0 & c0607=0) | (TMode=1 & thv_c0607=0)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); + ptr4:4 = &Dreg + (regInc * 24); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); + ptr4:4 = &Dreg - (regInc * 24); +@endif # ENDIAN = "big" + mult_dat8 = 8; + + *:1 mult_addr = *[register]:1 ptr1; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr2; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr3; + mult_addr = mult_addr + 1; + *:1 mult_addr = *[register]:1 ptr4; + mult_addr = mult_addr + 1; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 1; + ptr2 = ptr2 + 1; + ptr3 = ptr3 + 1; + ptr4 = ptr4 + 1; + goto ; + +} +vst4Dd: Dreg is Dreg & ((TMode=0 & c0607=1) | (TMode=1 & thv_c0607=1)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); + ptr4:4 = &Dreg + (regInc * 24); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); + ptr4:4 = &Dreg - (regInc * 24); +@endif # ENDIAN = "big" + mult_dat8 = 4; + + *:2 mult_addr = *[register]:2 ptr1; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr2; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr3; + mult_addr = mult_addr + 2; + *:2 mult_addr = *[register]:2 ptr4; + mult_addr = mult_addr + 2; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 2; + ptr2 = ptr2 + 2; + ptr3 = ptr3 + 2; + ptr4 = ptr4 + 2; + goto ; + +} +vst4Dd: Dreg is Dreg & ((TMode=0 & c0607=2) | (TMode=1 & thv_c0607=2)) & regInc +{ + ptr1:4 = &Dreg; +@if ENDIAN == "little" + ptr2:4 = &Dreg + (regInc * 8); + ptr3:4 = &Dreg + (regInc * 16); + ptr4:4 = &Dreg + (regInc * 24); +@else # ENDIAN == "big" + ptr2:4 = &Dreg - (regInc * 8); + ptr3:4 = &Dreg - (regInc * 16); + ptr4:4 = &Dreg - (regInc * 24); +@endif # ENDIAN = "big" + mult_dat8 = 2; + + *:4 mult_addr = *[register]:4 ptr1; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr2; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr3; + mult_addr = mult_addr + 4; + *:4 mult_addr = *[register]:4 ptr4; + mult_addr = mult_addr + 4; + mult_dat8 = mult_dat8 - 1; + if(mult_dat8 == 0) goto ; + ptr1 = ptr1 + 4; + ptr2 = ptr2 + 4; + ptr3 = ptr3 + 4; + ptr4 = ptr4 + 4; + goto ; + +} + +# Have to build only once, but because Dreg depends on regNum, have to reset it back to what it was to the start +buildVst4DdList: is counter=0 & vst4Dd [ regNum=regNum-4*regInc; ] +{ + build vst4Dd; +} +buildVst4DdList: Dreg^buildVst4DdList is counter=1 & Dreg & buildVst4DdList [ counter=0; regNum=regNum+regInc; ] { } buildVst4DdList: Dreg,buildVst4DdList is Dreg & buildVst4DdList [ counter=counter-1; regNum=regNum+regInc; ] { } vst4DdList: "{"^buildVst4DdList^"}" is TMode=0 & c0808=0 & D22 & c1215 & buildVst4DdList [ regNum=(D22<<4)+c1215-1; regInc=1; counter=4; ] { } # Single @@ -5802,13 +6288,27 @@ vst4DdList: "{"^buildVst4DdList^"}" is TMode=1 & thv_c0808=0 & thv_D22 & thv_c12 vst4DdList: "{"^buildVst4DdList^"}" is TMode=1 & thv_c0808=1 & thv_D22 & thv_c1215 & buildVst4DdList [ regNum=(thv_D22<<4)+thv_c1215-2; regInc=2; counter=4; ] { } # Double :vst4.^esize0607 vst4DdList,vst4RnAligned is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3 & c0003=15) | - ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=15) ) & vst4RnAligned & esize0607 & vst4DdList unimpl + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=15) ) & vst4RnAligned & esize0607 & vst4DdList +{ + mult_addr = vst4RnAligned; + build vst4DdList; +} :vst4.^esize0607 vst4DdList,vst4RnAligned^"!" is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3 & c0003=13) | - ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=13) ) & vst4RnAligned & esize0607 & vst4DdList unimpl + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3 & thv_c0003=13) ) & vst4RnAligned & esize0607 & vst4DdList +{ + mult_addr = vst4RnAligned; + build vst4DdList; + vst4RnAligned = vst4RnAligned + (8 * 4); +} :vst4.^esize0607 vst4DdList,vst4RnAligned,VRm is ( ($(AMODE) & ARMcond=0 & cond=15 & c2327=8 & c2021=0 & c0911=0 & c0607<3) | - ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3) ) & VRm & vst4RnAligned & esize0607 & vst4DdList unimpl + ($(TMODE_F) & thv_c2327=0x12 & thv_c2021=0 & thv_c0911=0 & thv_c0607<3) ) & VRm & vst4RnAligned & esize0607 & vst4DdList +{ + mult_addr = vst4RnAligned; + build vst4DdList; + vst4RnAligned = vst4RnAligned + VRm; +} ####### # VST4 (single 4-element structure from one lane) diff --git a/pypcode/processors/ARM/data/patterns/ARM_BE_patterns.xml b/pypcode/processors/ARM/data/patterns/ARM_BE_patterns.xml index cfd1eca3..31a095ff 100644 --- a/pypcode/processors/ARM/data/patterns/ARM_BE_patterns.xml +++ b/pypcode/processors/ARM/data/patterns/ARM_BE_patterns.xml @@ -67,7 +67,7 @@ 11100101 00101101 1110.... ........ 0xe24dd... 11100101 00101101 1110.... ........ 0x........ 0xe24dd... 0xe5 0x2d 0xe0 0x08 - 0xe1a0c00d 0xe92d.... + 0xe1a0c00d 0xe9 0x2. 11...... 0x.0 @@ -140,7 +140,7 @@ - 0xe1a0c00d 0xe92d.... + 0xe1a0c00d 0xe9 0x2. 11...... 0x.0 @@ -157,7 +157,7 @@ 0xe92d 0100.... ........ - + diff --git a/pypcode/processors/ARM/data/patterns/ARM_LE_patterns.xml b/pypcode/processors/ARM/data/patterns/ARM_LE_patterns.xml index dc113fa0..3f654adb 100644 --- a/pypcode/processors/ARM/data/patterns/ARM_LE_patterns.xml +++ b/pypcode/processors/ARM/data/patterns/ARM_LE_patterns.xml @@ -68,7 +68,7 @@ ........ 1110.... 00101101 11100101 0x..d.4de2 ........ 1110.... 00101101 11100101 0x........ 0x..d.4de2 0x08 0xe0 0x2d 0xe5 - 0x0dc0a0e1 0x....2de9 + 0x0dc0a0e1 0x.0 11...... 0x2. 0xe9 ........ 0100.... 00101101 11101001 @@ -156,7 +156,7 @@ - 0x0dc0a0e1 0x....2de9 + 0x0dc0a0e1 0x.0 11...... 0x2. 0xe9 @@ -173,7 +173,7 @@ 0x2de9 ........ 010..... - + diff --git a/pypcode/processors/Atmel/data/languages/avr8gcc.cspec b/pypcode/processors/Atmel/data/languages/avr8gcc.cspec index 5e35b798..bc27355a 100644 --- a/pypcode/processors/Atmel/data/languages/avr8gcc.cspec +++ b/pypcode/processors/Atmel/data/languages/avr8gcc.cspec @@ -40,49 +40,140 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/MCS96/data/languages/MCS96.sinc b/pypcode/processors/MCS96/data/languages/MCS96.sinc index cbc15f69..b75988fa 100644 --- a/pypcode/processors/MCS96/data/languages/MCS96.sinc +++ b/pypcode/processors/MCS96/data/languages/MCS96.sinc @@ -952,7 +952,7 @@ cc: "E" is cond=15 { tmp:1 = ($(Z) == 1); export tmp; } :POPF is op8=0xf3 { local result:2 = 0; pop(result); - PSW = result:1; + PSW = zext(result:1); local resultHi = result >> 8; INT_MASK = resultHi:1; } diff --git a/pypcode/processors/MIPS/data/languages/mips.ldefs b/pypcode/processors/MIPS/data/languages/mips.ldefs index 91b44bce..6b19a2f2 100644 --- a/pypcode/processors/MIPS/data/languages/mips.ldefs +++ b/pypcode/processors/MIPS/data/languages/mips.ldefs @@ -4,7 +4,7 @@ endian="big" size="32" variant="default" - version="1.8" + version="1.9" slafile="mips32be.sla" processorspec="mips32.pspec" manualindexfile="../manuals/mipsM16.idx" @@ -12,7 +12,7 @@ MIPS32 32-bit addresses, big endian, with mips16e - + @@ -24,7 +24,7 @@ endian="little" size="32" variant="default" - version="1.8" + version="1.9" slafile="mips32le.sla" processorspec="mips32.pspec" manualindexfile="../manuals/mipsM16.idx" @@ -32,7 +32,7 @@ MIPS32 32-bit addresses, little endian, with mips16e - + @@ -44,7 +44,7 @@ endian="big" size="32" variant="R6" - version="1.8" + version="1.9" slafile="mips32R6be.sla" processorspec="mips32R6.pspec" manualindexfile="../manuals/mipsMic.idx" @@ -60,7 +60,7 @@ endian="little" size="32" variant="R6" - version="1.8" + version="1.9" slafile="mips32R6le.sla" processorspec="mips32R6.pspec" manualindexfile="../manuals/mipsMic.idx" @@ -76,13 +76,13 @@ endian="big" size="64" variant="default" - version="1.8" + version="1.9" slafile="mips64be.sla" processorspec="mips64.pspec" manualindexfile="../manuals/mipsM16.idx" id="MIPS:BE:64:default"> MIPS64 64-bit addresses, big endian, with mips16e - + @@ -94,14 +94,14 @@ endian="little" size="64" variant="default" - version="1.8" + version="1.9" slafile="mips64le.sla" processorspec="mips64.pspec" manualindexfile="../manuals/mipsM16.idx" id="MIPS:LE:64:default"> MIPS64 64-bit addreses, little endian, with mips16e - - + + @@ -113,13 +113,13 @@ endian="big" size="64" variant="micro" - version="1.8" + version="1.9" slafile="mips64be.sla" processorspec="mips64micro.pspec" manualindexfile="../manuals/mipsMic.idx" id="MIPS:BE:64:micro"> MIPS64 64-bit addresses, big endian, with microMIPS - + @@ -128,14 +128,14 @@ endian="little" size="64" variant="micro" - version="1.8" + version="1.9" slafile="mips64le.sla" processorspec="mips64micro.pspec" manualindexfile="../manuals/mipsMic.idx" id="MIPS:LE:64:micro"> MIPS64 64-bit addresses, little endian, with microMIPS - - + + @@ -144,13 +144,13 @@ endian="big" size="64" variant="R6" - version="1.8" + version="1.9" slafile="mips64be.sla" processorspec="mips64R6.pspec" manualindexfile="../manuals/mipsMic.idx" id="MIPS:BE:64:R6"> MIPS64 Release-6 64-bit addresses, big endian, with microMIPS - + @@ -161,14 +161,14 @@ endian="little" size="64" variant="R6" - version="1.8" + version="1.9" slafile="mips64le.sla" processorspec="mips64R6.pspec" manualindexfile="../manuals/mipsMic.idx" id="MIPS:LE:64:R6"> MIPS64 Release-6 64-bit addresses, little endian, with microMIPS - - + + @@ -179,7 +179,7 @@ endian="big" size="32" variant="64-32addr" - version="1.8" + version="1.9" slafile="mips64be.sla" processorspec="mips64.pspec" manualindexfile="../manuals/mipsM16.idx" @@ -201,7 +201,7 @@ endian="little" size="32" variant="64-32addr" - version="1.8" + version="1.9" slafile="mips64le.sla" processorspec="mips64.pspec" manualindexfile="../manuals/mipsM16.idx" @@ -224,7 +224,7 @@ endian="little" size="32" variant="64-32addr-micro" - version="1.8" + version="1.9" slafile="mips64le.sla" processorspec="mips64micro.pspec" manualindexfile="../manuals/mipsMic.idx" @@ -244,7 +244,7 @@ endian="big" size="32" variant="64-32addr-micro" - version="1.8" + version="1.9" slafile="mips64be.sla" processorspec="mips64micro.pspec" manualindexfile="../manuals/mipsMic.idx" @@ -263,7 +263,7 @@ endian="big" size="32" variant="64-32addr-R6" - version="1.8" + version="1.9" slafile="mips64be.sla" processorspec="mips64R6.pspec" manualindexfile="../manuals/mipsMic.idx" @@ -284,7 +284,7 @@ endian="little" size="32" variant="64-32addr-R6" - version="1.8" + version="1.9" slafile="mips64le.sla" processorspec="mips64R6.pspec" manualindexfile="../manuals/mipsMic.idx" @@ -306,7 +306,7 @@ endian="big" size="32" variant="micro" - version="1.8" + version="1.9" slafile="mips32be.sla" processorspec="mips32micro.pspec" manualindexfile="../manuals/mipsMic.idx" @@ -321,7 +321,7 @@ endian="little" size="32" variant="micro" - version="1.8" + version="1.9" slafile="mips32le.sla" processorspec="mips32micro.pspec" manualindexfile="../manuals/mipsMic.idx" diff --git a/pypcode/processors/MIPS/data/languages/mips.sinc b/pypcode/processors/MIPS/data/languages/mips.sinc index a2660f78..c1e52917 100644 --- a/pypcode/processors/MIPS/data/languages/mips.sinc +++ b/pypcode/processors/MIPS/data/languages/mips.sinc @@ -448,6 +448,19 @@ define context contextreg ext_svrs_s0=(24,24) noflow ext_done=(25,25) noflow ext_delay=(26,27) noflow + + # 16e2 + ext_rb=(11,13) noflow + ext_imm_2426=(3, 5) + ext_imm_2526=(3,4) noflow + ext_imm_1620=(9,13) noflow + ext_imm_1920=(9,10) noflow + ext_imm_2124=(5, 8) noflow + ext_imm_2123=(6, 8) noflow + ext_imm_21=(8,8) noflow + ext_imm_2226=(3,7) noflow + + #below here is for micromips. Overlaps with mips16e ext_t4_name=(2,5) noflow ext_t4=(2,5) noflow diff --git a/pypcode/processors/MIPS/data/languages/mips16.sinc b/pypcode/processors/MIPS/data/languages/mips16.sinc index 3b7014cc..61175f27 100644 --- a/pypcode/processors/MIPS/data/languages/mips16.sinc +++ b/pypcode/processors/MIPS/data/languages/mips16.sinc @@ -64,7 +64,7 @@ define token m16instr (16) m16_code=(5,10) ; -attach variables [ m16_rx m16_ry m16_rz m16_mv_rz ] +attach variables [ m16_rx m16_ry m16_rz m16_mv_rz ext_rb ] [ s0 s1 v0 v1 a0 a1 a2 a3 ]; attach variables [ ext_m16r32 m16_i8_r32 ] [ @@ -143,7 +143,7 @@ EXT_IS8L3: val is ext_is_ext=0 & ext_value_1511 & ext_value_1005 & m16_is8_ EXT_IU8: val is ext_is_ext=1 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; } EXT_IU8: val is ext_is_ext=0 & m16_iu8_imm [val = m16_iu8_imm << 2; ] { export *[const]:2 val; } -EXT_LIU8: val is ext_is_ext=1 & m16_ri_z=0 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; } +EXT_LIU8: val is ext_is_ext=1 & ext_value_1511 & ext_value_1005 & m16_i8_imm [val = (ext_value_1511 << 11) | (ext_value_1005 << 5) | m16_i8_imm; ] { export *[const]:2 val; } EXT_LIU8: m16_iu8_imm is ext_is_ext=0 & m16_iu8_imm { export *[const]:2 m16_iu8_imm; } EXT_SHIFT: ext_value_sa40 is ext_is_ext=1 & ext_value_saz=0 & m16_shft_sa=0 & ext_value_sa40 { export *[const]:1 ext_value_sa40;} @@ -762,3 +762,261 @@ SAVE_TOP: SAVE_ARG^EXT_FRAME^SAVE_RA^SAVE_SREG^SAVE_STAT is EXT_FRAME & SAVE_RA tmp:2 = m16_rx:2; m16_rx = zext(tmp); } + + + +################ +# +# MIPS16e2 +# +# MIPS16e2 Application Specific Extension +# Technical Reference Manual +# +# Document #: MD01172 Rev 1.00 April 26, 2016 +# +################ + + +E2_REGOFF: imm is ext_imm_2124 & m16_i_imm [ imm = m16_i_imm | (ext_imm_2124 << 5);] { export *[const]:2 imm; } + + +:addiu m16_rx, gp, EXT_IS8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b00000 & ext_is_ext=1 & gp & m16_rx & m16_ri_z=1 & EXT_IS8 { + m16_rx = gp + sext(EXT_IS8); +} + +:andi m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=3 & EXT_LIU8 { + m16_rx = m16_rx & zext(EXT_LIU8); +} + +:cache ext_imm_1620, E2_REGOFF(m16_rx) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1620 & m16_op=0b11010 & m16_rx & m16_ri_z=5 & E2_REGOFF { + local tmp:$(REGSIZE) = m16_rx + sext(E2_REGOFF); + cacheOp(ext_imm_1620:1, tmp); +} + +:di is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00110 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0b01100 { + Status = Status & ~1; +} +:di m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00010 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0b01100 { + m16_ry = Status; + Status = Status & ~1; # clearing last bit (ffff..fffe == -2 signed) +} + +:dmt is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00110 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=1 { + # Clear VPEControl IE bit (bit 15) + VPEControl = VPEControl & ~0x8000; #VPEControl[15,1] = 0; +} +:dmt m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00010 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=1 { + # Clear VPEControl IE bit (bit 15) + m16_ry = VPEControl; VPEControl = VPEControl & ~0x8000; #VPEControl[15,1] = 0; +} + +:dvpe m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00010 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0 { + # Clear MVPControl EVP bit (bit 0) + m16_ry = MVPControl; MVPControl = MVPControl & ~0x1; +} +:dvpe is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0b001 & ext_imm_1620=0b00110 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0 { + # Clear MVPControl EVP bit (bit 0) + MVPControl = MVPControl & ~0x1; +} + +:ehb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0b00011 & ext_imm_21=0 & ext_imm_1620=0 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=4 & m16_shft_f=0 { +} + +:ei is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00111 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0b01100 { + Status = Status | 1; +} +:ei m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=0 & ext_imm_1620=0b00011 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0b01100 { + m16_ry = Status; + Status = Status | 1; +} + +:emt is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00111 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=1 { + # Set VPEControl TE bit (bit 15) + VPEControl = VPEControl | 0x8000; # VPEControl[15,1] = 1; +} +:emt m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00011 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=1 { + # Set VPEControl TE bit (bit 15) + m16_ry = VPEControl; VPEControl = VPEControl | 0x8000; # VPEControl[15,1] = 1; +} + +:evpe is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00111 & m16_op=0b01100 & m16_rx=0b111 & m16_ry=0 & m16_i_imm=0 { + # Set MVPControl EVP bit (bit 0)h + MVPControl = MVPControl | 0x1; +} +:evpe m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123=1 & ext_imm_1620=0b00011 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm=0 { + # Set MVPControl EVP bit (bit 0)h + m16_ry = MVPControl; + MVPControl = MVPControl | 0x1; +} + +:ext m16_ry, m16_rx, ext_imm_2226, ext_size is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=1 & ext_imm_1620 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0 [ ext_size = ext_imm_1620+1; ] { + local rs_tmp:$(REGSIZE) = m16_rx << ($(REGSIZE) * 8 - (ext_size + ext_imm_2226)); + rs_tmp = rs_tmp >> ($(REGSIZE) * 8 - ext_size); + m16_ry = zext(rs_tmp); +} +:ins m16_ry, m16_rx, ext_imm_2226, ins_size is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=1 & ext_imm_1620 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0 [ ins_size = ext_imm_1620 - ext_imm_2226 + 1; ] { + local tmpa:$(REGSIZE) = -1; + tmpa = tmpa >> ($(REGSIZE) * 8 - ins_size); + local tmpb:$(REGSIZE) = m16_rx & tmpa; + tmpa = tmpa << ext_imm_2226; + tmpa = ~tmpa; + tmpb = tmpb << ext_imm_2226; + m16_ry = (m16_ry & tmpa) | tmpb; + +} +:ins m16_ry, zero, ext_imm_2226, ins_size is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=0 & ext_imm_1620 & m16_op=0b00110 & m16_rx=0 & m16_ry & m16_shft_sa=1 & m16_shft_f=0 & zero [ ins_size = ext_imm_1620 - ext_imm_2226 + 1; ] { + local tmpa:$(REGSIZE) = -1; + tmpa = tmpa >> ($(REGSIZE) * 8 - ins_size); + tmpa = tmpa << ext_imm_2226; + tmpa = ~tmpa; + m16_ry = (m16_ry & tmpa); +} + +# LB/LBU/LH/LHU/LW - handled by mips16 + +:ll m16_rx, E2_REGOFF(ext_rb) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0 & ext_rb & m16_op=0b10010 & m16_rx & m16_ri_z=6 & E2_REGOFF { + local tmp:$(REGSIZE) = sext(E2_REGOFF); + tmp = tmp + ext_rb; + local tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + m16_rx = sext(*[ram]:4 tmpa); + lockload(tmp); +} + +:lui m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & m16_op=0b01101 & m16_rx & m16_ri_z=1 & EXT_LIU8 { + m16_rx = zext(EXT_LIU8) << 16; +} + +:lwl m16_rx, E2_REGOFF(ext_rb) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0 & ext_rb & m16_op=0b10010 & m16_rx & m16_ri_z=7 & E2_REGOFF { + local tmp:$(REGSIZE) = sext(E2_REGOFF); + tmp = tmp + ext_rb; + local shft:$(REGSIZE) = tmp & 0x3; + local addr:$(REGSIZE) = tmp - shft; + local valOrig:4 = m16_rx:$(SIZETO4) & (0xffffffff >> ((4-shft) * 8)); + local valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad << (shft * 8); + m16_rx = sext( valLoad | valOrig ); +} + +:lwr m16_rx, E2_REGOFF(ext_rb) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0b10 & ext_rb & m16_op=0b10010 & m16_rx & m16_ri_z=7 & E2_REGOFF { + local tmp:$(REGSIZE) = sext(E2_REGOFF); + tmp = tmp + ext_rb; + local shft:$(REGSIZE) = tmp & 0x3; + local addr:$(REGSIZE) = tmp - shft; + local valOrig:4 = m16_rx:$(SIZETO4) & (0xffffffff << ((shft+1) * 8)); + local valLoad:4 = 0; + MemSrcCast(valLoad,addr); + valLoad = valLoad >> ((3-shft) * 8); + m16_rx = sext( valOrig | valLoad ); +} + +:mfc0 m16_ry, m16_i_imm, ext_imm_2123 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=0 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm { + m16_ry = getCopReg(0:1,m16_i_imm:1,ext_imm_2123:1); +} +:mtc0 m16_ry, m16_i_imm, ext_imm_2123 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2426=0 & ext_imm_2123 & ext_imm_1620=1 & m16_op=0b01100 & m16_rx=0b111 & m16_ry & m16_i_imm { + setCopReg(0:1,m16_ry,m16_i_imm:1,ext_imm_2123:1); +} + +:movz m16_rx, m16_ry, ext_rb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0b10 { + if(m16_ry != 0) goto inst_next; + m16_rx = ext_rb; +} + +:movz m16_rx, zero, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb=0 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=1 & m16_shft_f=0b10 & zero { + if(m16_ry != 0) goto inst_next; + m16_rx = 0; +} + +:movn m16_rx, m16_ry, ext_rb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0b10 { + if(m16_ry == 0) goto inst_next; + m16_rx = ext_rb; +} + +:movn m16_rx, zero, m16_ry is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb=0 & m16_op=0b00110 & m16_rx & m16_ry & m16_shft_sa=2 & m16_shft_f=0b10 & zero { + if(m16_ry == 0) goto inst_next; + m16_rx = 0; +} + +:movtn m16_rx, zero is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=6 & m16_shft_f=0b10 & zero { + if(t8 == 0) goto inst_next; + m16_rx = 0; +} + +:movtn m16_rx, ext_rb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=6 & m16_shft_f=0b10 { + if(t8 == 0) goto inst_next; + m16_rx = ext_rb; +} + +:movtz m16_rx, zero is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=5 & m16_shft_f=0b10 & zero { + if(t8 != 0) goto inst_next; + m16_rx = 0; +} + +:movtz m16_rx, ext_rb is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=1 & ext_imm_1920=0 & ext_rb & m16_op=0b00110 & m16_rx & m16_rr_z=0 & m16_shft_sa=5 & m16_shft_f=0b10 { + if(t8 != 0) goto inst_next; + m16_rx = ext_rb; +} + +:pause is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0b00101 & ext_imm_21=0 & ext_imm_1620=0 & m16_op=0b00110 & m16_rx=0 & m16_rr_z=0 & m16_shft_sa=6 & m16_shft_f=0 { + wait(); +} + +:pref ext_imm_1620, E2_REGOFF(m16_rx) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1620 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=4 & E2_REGOFF { + local tmp:$(REGSIZE) = m16_rx + sext(E2_REGOFF); + prefetch(tmp, ext_imm_1620:1); +} + +:ori m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=2 & EXT_LIU8 { + m16_rx = m16_rx | zext(EXT_LIU8); +} + +:rdhwr m16_ry, ext_imm_1620 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226=0 & ext_imm_21=0 & ext_imm_1620 & m16_op=0b00110 & m16_rx=0 & m16_ry & m16_shft_sa=3 & m16_shft_f=0 { + m16_ry = getHWRegister(ext_imm_1620:1); +} + +# SB/SH/SW - handled by mips16 + +:sc m16_rx, E2_REGOFF(ext_rb) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=6 & E2_REGOFF{ + local tmp:$(REGSIZE) = sext(E2_REGOFF); + tmp = tmp + ext_rb; + lockwrite(tmp); + local tmpa:$(ADDRSIZE) = 0; + ValCast(tmpa,tmp); + *[ram]:4 tmpa = m16_rx; + m16_rx = 1; +} + +:swl m16_rx, E2_REGOFF(ext_rb) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0b00 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=7 & E2_REGOFF{ + local tmp:$(REGSIZE) = sext(E2_REGOFF); + tmp = tmp + ext_rb; + local tmpRT:4 = m16_rx:$(SIZETO4); + local shft:$(REGSIZE) = tmp & 0x3; + local addr:$(REGSIZE) = tmp - shft; + local valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff << ((4-shft) * 8)); + local valStore:4 = (tmpRT >> (shft * 8)) | valOrig; + MemDestCast(addr,valStore); +} + +:swr m16_rx, E2_REGOFF(ext_rb) is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2526=0 & ext_imm_1920=0b10 & ext_rb & m16_op=0b11010 & m16_rx & m16_ri_z=7 & E2_REGOFF { + local tmp:$(REGSIZE) = sext(E2_REGOFF); + tmp = tmp + ext_rb; + local tmpRT:4 = m16_rx:$(SIZETO4); + local shft:$(REGSIZE) = tmp & 0x3; + local addr:$(REGSIZE) = tmp - shft; + local valOrig:4 = 0; + MemSrcCast(valOrig,addr); + valOrig = valOrig & (0xffffffff >> ((shft+1) * 8)); + local valStore:4 = (tmpRT << ((3-shft)*8)) | valOrig; + MemDestCast(addr,valStore); +} + +:sync ext_imm_2226 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & ext_imm_2226 & ext_imm_21=0 & ext_imm_1620=0 & m16_op=0b00110 & m16_rx=0 & m16_ry=0 & m16_shft_sa=5 & m16_shft_f=0b00 { + SYNC(ext_imm_2226:1); +} + +:xori m16_rx, EXT_LIU8 is ISA_MODE=1 & RELP=1 & ext_isjal=0 & ext_is_ext=1 & m16_op=0b01101 & m16_rx & m16_ri_z=4 & EXT_LIU8 { + m16_rx = m16_rx ^ zext(EXT_LIU8); +} diff --git a/pypcode/processors/MIPS/data/languages/mips32be_eabi.cspec b/pypcode/processors/MIPS/data/languages/mips32_eabi.cspec similarity index 68% rename from pypcode/processors/MIPS/data/languages/mips32be_eabi.cspec rename to pypcode/processors/MIPS/data/languages/mips32_eabi.cspec index 7236a930..235b5351 100644 --- a/pypcode/processors/MIPS/data/languages/mips32be_eabi.cspec +++ b/pypcode/processors/MIPS/data/languages/mips32_eabi.cspec @@ -2,7 +2,12 @@ + + + + + @@ -65,6 +70,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -73,9 +106,21 @@ - - - + + + + + + + + + + + + + + + @@ -97,21 +142,11 @@ - - - - - - - - - - - - - - - + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips32be.cspec b/pypcode/processors/MIPS/data/languages/mips32be.cspec index c85f28c6..bd621b77 100644 --- a/pypcode/processors/MIPS/data/languages/mips32be.cspec +++ b/pypcode/processors/MIPS/data/languages/mips32be.cspec @@ -25,6 +25,7 @@ + @@ -47,6 +48,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -55,9 +102,25 @@ - - + + + + + + + + + + + + + + + + + + @@ -72,12 +135,24 @@ + + + + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips32le.cspec b/pypcode/processors/MIPS/data/languages/mips32le.cspec index aa246286..13e5c299 100644 --- a/pypcode/processors/MIPS/data/languages/mips32le.cspec +++ b/pypcode/processors/MIPS/data/languages/mips32le.cspec @@ -47,6 +47,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -55,9 +93,25 @@ - - + + + + + + + + + + + + + + + + + + @@ -72,12 +126,24 @@ + + + + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips32le_eabi.cspec b/pypcode/processors/MIPS/data/languages/mips32le_eabi.cspec deleted file mode 100644 index f4a66920..00000000 --- a/pypcode/processors/MIPS/data/languages/mips32le_eabi.cspec +++ /dev/null @@ -1,123 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/MIPS/data/languages/mips64.cspec b/pypcode/processors/MIPS/data/languages/mips64.cspec deleted file mode 100644 index e654191c..00000000 --- a/pypcode/processors/MIPS/data/languages/mips64.cspec +++ /dev/null @@ -1,111 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/MIPS/data/languages/mips64be.cspec b/pypcode/processors/MIPS/data/languages/mips64be.cspec new file mode 100644 index 00000000..dbcf456c --- /dev/null +++ b/pypcode/processors/MIPS/data/languages/mips64be.cspec @@ -0,0 +1,189 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/MIPS/data/languages/mips64le.cspec b/pypcode/processors/MIPS/data/languages/mips64le.cspec new file mode 100644 index 00000000..6cebc649 --- /dev/null +++ b/pypcode/processors/MIPS/data/languages/mips64le.cspec @@ -0,0 +1,173 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/NDS32/data/languages/lsmw.sinc b/pypcode/processors/NDS32/data/languages/lsmw.sinc new file mode 100644 index 00000000..bff5e758 --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/lsmw.sinc @@ -0,0 +1,125 @@ +Dreg: a0 is a0 & regNum=0 { export a0; } +Dreg: a1 is a1 & regNum=1 { export a1; } +Dreg: a2 is a2 & regNum=2 { export a2; } +Dreg: a3 is a3 & regNum=3 { export a3; } +Dreg: a4 is a4 & regNum=4 { export a4; } +Dreg: a5 is a5 & regNum=5 { export a5; } +Dreg: s0 is s0 & regNum=6 { export s0; } +Dreg: s1 is s1 & regNum=7 { export s1; } +Dreg: s2 is s2 & regNum=8 { export s2; } +Dreg: s3 is s3 & regNum=9 { export s3; } +Dreg: s4 is s4 & regNum=10 { export s4; } +Dreg: s5 is s5 & regNum=11 { export s5; } +Dreg: s6 is s6 & regNum=12 { export s6; } +Dreg: s7 is s7 & regNum=13 { export s7; } +Dreg: s8 is s8 & regNum=14 { export s8; } +Dreg: ta is ta & regNum=15 { export ta; } +Dreg: t0 is t0 & regNum=16 { export t0; } +Dreg: t1 is t1 & regNum=17 { export t1; } +Dreg: t2 is t2 & regNum=18 { export t2; } +Dreg: t3 is t3 & regNum=19 { export t3; } +Dreg: t4 is t4 & regNum=20 { export t4; } +Dreg: t5 is t5 & regNum=21 { export t5; } +Dreg: t6 is t6 & regNum=22 { export t6; } +Dreg: t7 is t7 & regNum=23 { export t7; } +Dreg: t8 is t8 & regNum=24 { export t8; } +Dreg: t9 is t9 & regNum=25 { export t9; } +Dreg: p0 is p0 & regNum=26 { export p0; } +Dreg: p1 is p1 & regNum=27 { export p1; } +Dreg: fp is fp & regNum=28 { export fp; } +Dreg: gp is gp & regNum=29 { export gp; } +Dreg: lp is lp & regNum=30 { export lp; } +Dreg: sp is sp & regNum=31 { export sp; } + +macro Smwad(reg) { + mult_addr = mult_addr - 4; + *mult_addr = reg; +} + +macro LmwOp(reg) { + reg = *mult_addr; +} + +macro SmwOp(reg) { + *mult_addr = reg; +} + +macro MwDec() { mult_addr = mult_addr - 4; } +macro MwInc() { mult_addr = mult_addr + 4; } + +Lsmw_id: is LsmwId=0 { MwInc(); } +Lsmw_id: is LsmwId=1 { MwDec(); } + +Lmw.fp: fp is Lsmw_id & LsmwBa=0 & Enable4_fp=1 & fp { LmwOp(fp); build Lsmw_id; } +Lmw.fp: fp is Lsmw_id & LsmwBa=1 & Enable4_fp=1 & fp { build Lsmw_id; LmwOp(fp); } +Lmw.fp: is Enable4_fp=0 { } +Lmw.gp: gp is Lsmw_id & LsmwBa=0 & Enable4_gp=1 & gp { LmwOp(gp); build Lsmw_id; } +Lmw.gp: gp is Lsmw_id & LsmwBa=1 & Enable4_gp=1 & gp { build Lsmw_id; LmwOp(gp); } +Lmw.gp: is Enable4_gp=0 { } +Lmw.lp: lp is Lsmw_id & LsmwBa=0 & Enable4_lp=1 & lp { LmwOp(lp); build Lsmw_id; } +Lmw.lp: lp is Lsmw_id & LsmwBa=1 & Enable4_lp=1 & lp { build Lsmw_id; LmwOp(lp); } +Lmw.lp: is Enable4_lp=0 { } +Lmw.sp: sp is Lsmw_id & LsmwBa=0 & Enable4_sp=1 & sp { LmwOp(sp); build Lsmw_id; } +Lmw.sp: sp is Lsmw_id & LsmwBa=1 & Enable4_sp=1 & sp { build Lsmw_id; LmwOp(sp); } +Lmw.sp: is Enable4_sp=0 { } + +# Terminating condition +LmwReg: Dreg is LsmwId=0 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; LmwOp(Dreg); MwInc(); } +LmwReg: Dreg is LsmwId=1 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; LmwOp(Dreg); MwDec(); } + +LmwReg: Dreg is LsmwId=0 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; MwInc(); LmwOp(Dreg); } +LmwReg: Dreg is LsmwId=1 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; MwDec(); LmwOp(Dreg); } + +LmwReg: Dreg, LmwReg is LsmwId=0 & LsmwBa=0 & Dreg & LmwReg [ counter = counter-1; regNum=regNum+1;] { LmwOp(Dreg); MwInc(); build LmwReg; } +LmwReg: Dreg, LmwReg is LsmwId=1 & LsmwBa=0 & Dreg & LmwReg [ counter = counter-1; regNum=regNum-1;] { LmwOp(Dreg); MwDec(); build LmwReg; } + +LmwReg: Dreg, LmwReg is LsmwId=0 & LsmwBa=1 & Dreg & LmwReg [ counter = counter-1; regNum=regNum+1;] { MwInc(); LmwOp(Dreg); build LmwReg; } +LmwReg: Dreg, LmwReg is LsmwId=1 & LsmwBa=1 & Dreg & LmwReg [ counter = counter-1; regNum=regNum-1;] { MwDec(); LmwOp(Dreg); build LmwReg; } + +# Initial conditions +Lmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp) ... & LmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build LmwReg; build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; } +Lmw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp) ... & LmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; build LmwReg; } +Lmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; } +Lmw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; } + +Lmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp) ... & LmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build LmwReg; build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; } +Lmwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp) ... & LmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; build LmwReg; } +Lmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Lmw.fp & Lmw.gp & Lmw.lp & Lmw.sp { build Lmw.sp; build Lmw.lp; build Lmw.gp; build Lmw.fp; } +Lmwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Lmw.sp & Lmw.lp & Lmw.gp & Lmw.fp { build Lmw.fp; build Lmw.gp; build Lmw.lp; build Lmw.sp; } + +Smw.fp: fp is Lsmw_id & LsmwBa=0 & Enable4_fp=1 & fp { SmwOp(fp); build Lsmw_id; } +Smw.fp: fp is Lsmw_id & LsmwBa=1 & Enable4_fp=1 & fp { build Lsmw_id; SmwOp(fp); } +Smw.fp: is Enable4_fp=0 { } +Smw.gp: gp is Lsmw_id & LsmwBa=0 & Enable4_gp=1 & gp { SmwOp(gp); build Lsmw_id; } +Smw.gp: gp is Lsmw_id & LsmwBa=1 & Enable4_gp=1 & gp { build Lsmw_id; SmwOp(gp); } +Smw.gp: is Enable4_gp=0 { } +Smw.lp: lp is Lsmw_id & LsmwBa=0 & Enable4_lp=1 & lp { SmwOp(lp); build Lsmw_id; } +Smw.lp: lp is Lsmw_id & LsmwBa=1 & Enable4_lp=1 & lp { build Lsmw_id; SmwOp(lp); } +Smw.lp: is Enable4_lp=0 { } +Smw.sp: sp is Lsmw_id & LsmwBa=0 & Enable4_sp=1 & sp { SmwOp(sp); build Lsmw_id; } +Smw.sp: sp is Lsmw_id & LsmwBa=1 & Enable4_sp=1 & sp { build Lsmw_id; SmwOp(sp); } +Smw.sp: is Enable4_sp=0 { } + +# Terminating condition +SmwReg: Dreg is LsmwId=0 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; SmwOp(Dreg); MwInc(); } +SmwReg: Dreg is LsmwId=1 & LsmwBa=0 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; SmwOp(Dreg); MwDec(); } + +SmwReg: Dreg is LsmwId=0 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum+1;] { build Dreg; MwInc(); SmwOp(Dreg); } +SmwReg: Dreg is LsmwId=1 & LsmwBa=1 & Dreg & counter=1 [regNum=regNum-1;] { build Dreg; MwDec(); SmwOp(Dreg); } + +SmwReg: Dreg, SmwReg is LsmwId=0 & LsmwBa=0 & Dreg & SmwReg [ counter = counter-1; regNum=regNum+1;] { build Dreg; SmwOp(Dreg); MwInc(); build SmwReg; } +SmwReg: Dreg, SmwReg is LsmwId=1 & LsmwBa=0 & Dreg & SmwReg [ counter = counter-1; regNum=regNum-1;] { build Dreg; SmwOp(Dreg); MwDec(); build SmwReg; } + +SmwReg: Dreg, SmwReg is LsmwId=0 & LsmwBa=1 & Dreg & SmwReg [ counter = counter-1; regNum=regNum+1;] { build Dreg; MwInc(); SmwOp(Dreg); build SmwReg; } +SmwReg: Dreg, SmwReg is LsmwId=1 & LsmwBa=1 & Dreg & SmwReg [ counter = counter-1; regNum=regNum-1;] { build Dreg; MwDec(); SmwOp(Dreg); build SmwReg; } + +# Initial conditions +Smw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp) ... & SmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build SmwReg; build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; } +Smw.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp) ... & SmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; build SmwReg; } +Smw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; } +Smw.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; } + +Smwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp) ... & SmwReg [ regNum=LsmwRb_-1; counter=LsmwRe_-LsmwRb_+1; ] { build SmwReg; build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; } +Smwa.regs: is (LsmwRe_ & LsmwRb_ & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp) ... & SmwReg [ regNum=LsmwRe_+1; counter=LsmwRe_-LsmwRb_+1; ] { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; build SmwReg; } +Smwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=0 & Smw.fp & Smw.gp & Smw.lp & Smw.sp { build Smw.sp; build Smw.lp; build Smw.gp; build Smw.fp; } +Smwa.regs: is LsmwRe_=0x1f & LsmwRb_=0x1f & LsmwId=1 & Smw.sp & Smw.lp & Smw.gp & Smw.fp { build Smw.fp; build Smw.gp; build Smw.lp; build Smw.sp; } diff --git a/pypcode/processors/NDS32/data/languages/nds32.cspec b/pypcode/processors/NDS32/data/languages/nds32.cspec new file mode 100644 index 00000000..ed3a93b0 --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32.cspec @@ -0,0 +1,115 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/NDS32/data/languages/nds32.dwarf b/pypcode/processors/NDS32/data/languages/nds32.dwarf new file mode 100644 index 00000000..b254e363 --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32.dwarf @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/pypcode/processors/NDS32/data/languages/nds32.ldefs b/pypcode/processors/NDS32/data/languages/nds32.ldefs new file mode 100644 index 00000000..8ee0ac46 --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32.ldefs @@ -0,0 +1,33 @@ + + + + + NDS32 default processor 32-bit big-endian + + + + + + NDS32 default processor 32-bit little-endian + + + + + + diff --git a/pypcode/processors/NDS32/data/languages/nds32.opinion b/pypcode/processors/NDS32/data/languages/nds32.opinion new file mode 100644 index 00000000..bf744db1 --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/pypcode/processors/NDS32/data/languages/nds32.pspec b/pypcode/processors/NDS32/data/languages/nds32.pspec new file mode 100644 index 00000000..d70bdf4a --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32.pspec @@ -0,0 +1,155 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pypcode/processors/NDS32/data/languages/nds32.sinc b/pypcode/processors/NDS32/data/languages/nds32.sinc new file mode 100644 index 00000000..141183a3 --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32.sinc @@ -0,0 +1,1625 @@ +### General ### + +define endian=big; +define alignment=2; +define space ram type=ram_space size=4 wordsize=1 default; +define space register type=register_space size=4; + +define space csreg type=ram_space size=2 wordsize=4; + +@define CSR_REG_START "0x0000" + +define register offset=0 size=4 +[a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 s6 s7 s8 ta t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 p0 p1 fp gp lp sp]; + +define register offset=0x90 size=4 +[pc mult_addr mult_inc]; + +define register offset=0x100 size=8 +[d0 d1]; + +define register offset=0x100 size=4 +[d0.hi d0.lo d1.hi d1.lo]; + +define register offset=0x200 size=4 +[ itb lb lc le ifc_lp + fpcsr fpcfg +]; + +define register offset=0x1000 size=4 +[ fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7 + fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15 + fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23 + fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31 +]; + +define register offset=0x1000 size=8 +[ fd0 fd1 fd2 fd3 fd4 fd5 fd6 fd7 + fd8 fd9 fd10 fd11 fd12 fd13 fd14 fd15 + fd16 fd17 fd18 fd19 fd20 fd21 fd22 fd23 + fd24 fd25 fd26 fd27 fd28 fd29 fd30 fd31 +]; + +define csreg offset=0x0a9 size=4 +[ + ipc +]; + +define register offset=0x300 size=8 contextreg; +define context contextreg + counter = (22,26) + regNum = (27,31) # register for load/store multiple instructions +; + +define token instr32(32) + OpSz = (31, 31) + Opc = (25, 30) + Rt = (20, 24) + Fst = (20, 24) + Fdt = (20, 24) + Rth = (21, 24) + Rtl = (21, 24) + Ra = (15, 19) + Fsa = (15, 19) + Fda = (15, 19) + Rb = (10, 14) + Fsb = (10, 14) + Fdb = (10, 14) + Rd = (5, 9) + Rs = (5, 9) + Sub5 = (0, 4) + Sub6 = (0, 5) + Sub7 = (0, 6) + Sub8 = (0, 7) + Sub3 = (7, 9) + fop4 = (6, 9) + cop4 = (0, 3) + f2op = (10, 14) + fcnd = (7, 9) + cmpe = (6, 6) + fbi = (7, 7) + cpn = (13, 14) + fsbi = (12, 12) + Imm8u = (7,14) + Imm5u = (10, 14) + Imm5s = (10, 14) signed + Br1t = (14, 14) + Br2t = (16, 19) + Alu2Mod = (6, 9) + Dtl = (22, 24) + Dt = (21, 21) + Dtlow = (21, 21) + Dthigh = (21, 21) + Dtr = (20, 20) + JIt = (24, 24) + Imm19s = (0, 18) signed + Imm18s = (0, 17) signed + Imm17s = (0, 16) signed + Imm16s = (0, 15) signed + Imm14s = (0, 13) signed + Imm15u = (0, 14) + Imm15s = (0, 14) signed + Imm20u = (0, 19) + Imm20s = (0, 19) signed + Imm24s = (0, 23) signed + Imm12s = (0, 11) signed + Imm11s = (8, 18) signed + Imm8s = (0, 7) signed + sv = (8, 9) + SrIdx = (10, 19) + Swid = (5, 19) + + CctlZ = (11, 14) + CctlLevel = (10, 10) + CctlSub = (5, 9) + + MsyncZ = (8, 19) + MsyncSub = (5, 7) + + DtIt = (8, 9) + Jz = (6, 7) + JrHint = (5, 5) + + ToggleL = (21, 24) + Toggle = (20, 20) + + Usr = (15, 19) + Group = (10, 14) + + DprefD = (24, 24) + DprefSub = (20, 23) + + TlbopSub = (5, 9) + + StandbyZ = (7, 9) + StandbySub = (5, 6) + + GpSub1 = (19, 19) + GpSub2 = (18, 19) + GpSub3 = (17, 19) + + sh = (5, 9) + + Bxxc = (19, 19) + + LsmwRa = (15, 19) + LsmwRb = (20, 24) + LsmwRb_ = (20, 24) + LsmwRe = (10, 14) + LsmwRe_ = (10, 14) + Enable4 = (6, 9) + Enable4_fp = (9, 9) + Enable4_gp = (8, 8) + Enable4_lp = (7, 7) + Enable4_sp = (6, 6) + LsmwLs = (5, 5) + LsmwBa = (4, 4) + LsmwId = (3, 3) + LsmwM = (2, 2) + LsmwSub = (0, 1) +; + +attach variables [Rt Rs Ra Rb Rd LsmwRa LsmwRb LsmwRe] [ + a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 s6 s7 s8 ta t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 p0 p1 fp gp lp sp +]; + +attach variables [Rtl] [ + a0 a2 a4 s0 s2 s4 s6 s8 t0 t2 t4 t6 t8 p0 fp lp +]; + +attach variables [Rth] [ + a1 a3 a5 s1 s3 s5 s7 ta t1 t3 t5 t7 t9 p1 gp sp +]; + +attach variables [Dt] [ + d0 d1 +]; + +attach variables [Dtlow] [ + d0.lo d1.lo +]; + +attach variables [Dthigh] [ + d0.hi d1.hi +]; + +attach variables [ Fst Fsa Fsb ] +[ fs0 fs1 fs2 fs3 fs4 fs5 fs6 fs7 + fs8 fs9 fs10 fs11 fs12 fs13 fs14 fs15 + fs16 fs17 fs18 fs19 fs20 fs21 fs22 fs23 + fs24 fs25 fs26 fs27 fs28 fs29 fs30 fs31 +]; + +attach variables [ Fdt Fda Fdb ] +[ fd0 fd1 fd2 fd3 fd4 fd5 fd6 fd7 + fd8 fd9 fd10 fd11 fd12 fd13 fd14 fd15 + fd16 fd17 fd18 fd19 fd20 fd21 fd22 fd23 + fd24 fd25 fd26 fd27 fd28 fd29 fd30 fd31 +]; + +@define I32 "(OpSz=0)" +@define LBGP "(Opc=0b010111)" +@define LWC "(Opc=0b011000)" +@define SWC "(Opc=0b011001)" +@define LDC "(Opc=0b011010)" +@define SDC "(Opc=0b011011)" +@define LSMW "(Opc=0b011101)" +@define MEM "(Opc=0b011100)" +@define HWGP "(Opc=0b011110)" +@define SBGP "(Opc=0b011111)" +@define ALU_1 "(Opc=0b100000)" +@define ALU_2 "(Opc=0b100001)" +@define JI "(Opc=0b100100)" +@define JREG "(Opc=0b100101)" +@define BR1 "(Opc=0b100110)" +@define BR2 "(Opc=0b100111)" +@define BR3 "(Opc=0b101101)" +@define MISC "(Opc=0b110010)" +@define COP "(Opc=0b110101)" +@define SIMD "(Opc=0b111000)" + +@define ALU2Z "(Alu2Mod=0b0000)" +@define GPR "(Alu2Mod=0b0001)" + + +### ALU Instruction with Immediate ### + +:addi Rt, Ra, Imm15s is $(I32) & Opc=0b101000 & Rt & Ra & Imm15s { Rt = Ra + Imm15s; } +:subri Rt, Ra, Imm15s is $(I32) & Opc=0b101001 & Rt & Ra & Imm15s { Rt = Imm15s - Ra; } +:andi Rt, Ra, Imm15u is $(I32) & Opc=0b101010 & Rt & Ra & Imm15u { Rt = Ra & Imm15u; } +:ori Rt, Ra, Imm15u is $(I32) & Opc=0b101100 & Rt & Ra & Imm15u { Rt = Ra | Imm15u; } +:xori Rt, Ra, Imm15u is $(I32) & Opc=0b101011 & Rt & Ra & Imm15u { Rt = Ra ^ Imm15u; } +:slti Rt, Ra, Imm15s is $(I32) & Opc=0b101110 & Rt & Ra & Imm15s { Rt = zext(Ra < Imm15s); } +:sltsi Rt, Ra, Imm15s is $(I32) & Opc=0b101111 & Rt & Ra & Imm15s { Rt = zext(Ra s< Imm15s); } +:movi Rt, Imm20s is $(I32) & Opc=0b100010 & Rt & Imm20s { Rt = Imm20s; } +:sethi Rt, Imm20u is $(I32) & Opc=0b100011 & Rt & Imm20u { Rt = Imm20u << 12;} + + +### ALU Instruction ### + +:add Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00000 { Rt = Ra + Rb; } +:sub Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00001 { Rt = Ra - Rb; } +:and Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00010 { Rt = Ra & Rb; } +:xor Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00011 { Rt = Ra ^ Rb; } +:or Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00100 { Rt = Ra | Rb; } +:nor Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00101 { Rt = ~(Ra | Rb); } +:slt Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00110 { Rt = zext(Ra < Rb); } +:slts Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b00111 { Rt = zext(Ra s< Rb); } +:sva Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11000 { Rt = zext(scarry(Ra, Rb)); } +:svs Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11001 { Rt = zext(sborrow(Ra, Rb)); } +:seb Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10000 { local tmp = Ra; Rt = sext(tmp:1); } +:seh Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10001 { local tmp = Ra; Rt = sext(tmp:2); } +:zeb Rt, Ra is $(I32) & Opc=0b101010 & Rt & Ra & Imm15u=0xff { local tmp = Ra; Rt = zext(tmp:1); } +:zeh Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10011 { local tmp = Ra; Rt = zext(tmp:2); } +:wsbh Rt, Ra is $(I32) & $(ALU_1) & Rt & Ra & Rb=0b00000 & Rd=0 & Sub5=0b10100 +{ + Rt = ((Ra & 0x000000ff) << 8) + | ((Ra & 0x0000ff00) >> 8) + | ((Ra & 0x00ff0000) << 8) + | ((Ra & 0xff000000) >> 8); +} + + +### Shifter Instruction ### + +:slli Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01000 { Rt = Ra << Imm5u; } +:srli Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01001 { Rt = Ra >> Imm5u; } +:srai Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01010 { Rt = Ra s>> Imm5u; } +:rotri Rt, Ra, Imm5u is $(I32) & $(ALU_1) & Rt & Ra & Imm5u & Rd=0 & Sub5=0b01011 { Rt = (Ra >> Imm5u) | (Ra << (32 - Imm5u)); } +:sll Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01100 { tmp:4 = Rb & 0b11111; Rt = Ra << tmp; } +:srl Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01101 { tmp:4 = Rb & 0b11111; Rt = Ra >> tmp; } +:sra Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01110 { tmp:4 = Rb & 0b11111; Rt = Ra s>> tmp; } +:rotr Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b01111 { tmp:4 = Rb & 0b11111; Rt = (Ra >> tmp) | (Ra << (32 - tmp)); } + + +### Multiply Instruction ### + +:mul Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b100100 { Rt = Ra * Rb; } +:mults64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101000 { Dt = sext(Ra) * sext(Rb); } +:mult64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101001 { Dt = zext(Ra) * zext(Rb); } +:madds64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101010 { Dt = Dt + (sext(Ra) * sext(Rb)); } +:madd64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101011 { Dt = Dt + (zext(Ra) * zext(Rb)); } +:msubs64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101100 { Dt = Dt - (sext(Ra) * sext(Rb)); } +:msub64 Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101101 { Dt = Dt - (zext(Ra) * zext(Rb)); } +:mult32 Dtlow, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dtlow & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b110001 { Dtlow = Ra * Rb; } +:madd32 Dtlow, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dtlow & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b110011 { Dtlow = Dtlow + (Ra * Rb); } +:msub32 Dtlow, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dtlow & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b110101 { Dtlow = Dtlow - (Ra * Rb); } + + +# Group 0 +UsrName: d0.lo is Group=0 & Usr=0 & d0.lo { export d0.lo; } +UsrName: d0.hi is Group=0 & Usr=1 & d0.hi { export d0.hi; } +UsrName: d1.lo is Group=0 & Usr=2 & d1.lo { export d1.lo; } +UsrName: d1.hi is Group=0 & Usr=3 & d1.hi { export d1.hi; } +UsrName: lb is Group=0 & Usr=25 & lb { export lb; } +UsrName: le is Group=0 & Usr=26 & le { export le; } +UsrName: lc is Group=0 & Usr=27 & lc { export lc; } +UsrName: itb is Group=0 & Usr=28 & itb { export itb; } +UsrName: ifc_lp is Group=0 & Usr=29 & ifc_lp { export ifc_lp; } +#UsrName: pc is Group=0 & Usr=31 & pc { export pc; } # handled separately + +# Group 1 +UsrName: "dma_cfg" is Group=1 & Usr=0 { tmp:2 = 0x280; export *[csreg]:4 tmp; } +UsrName: "dma_gcsw" is Group=1 & Usr=1 { tmp:2 = 0x288; export *[csreg]:4 tmp; } +UsrName: "dma_chnsel" is Group=1 & Usr=2 { tmp:2 = 0x290; export *[csreg]:4 tmp; } +UsrName: "dma_act" is Group=1 & Usr=3 { tmp:2 = 0x298; export *[csreg]:4 tmp; } +UsrName: "dma_setup" is Group=1 & Usr=4 { tmp:2 = 0x2a0; export *[csreg]:4 tmp; } +UsrName: "dma_isaddr" is Group=1 & Usr=5 { tmp:2 = 0x2a8; export *[csreg]:4 tmp; } +UsrName: "dma_esaddr" is Group=1 & Usr=6 { tmp:2 = 0x2b0; export *[csreg]:4 tmp; } +UsrName: "dma_tcnt" is Group=1 & Usr=7 { tmp:2 = 0x2b8; export *[csreg]:4 tmp; } +UsrName: "dma_status" is Group=1 & Usr=8 { tmp:2 = 0x2c0; export *[csreg]:4 tmp; } +UsrName: "dma_2dset" is Group=1 & Usr=9 { tmp:2 = 0x2c8; export *[csreg]:4 tmp; } +UsrName: "dma_rcnt" is Group=1 & Usr=23 { tmp:2 = 0x2b9; export *[csreg]:4 tmp; } +UsrName: "dma_hstatus" is Group=1 & Usr=24 { tmp:2 = 0x2c1; export *[csreg]:4 tmp; } +UsrName: "dma_2dsctl" is Group=1 & Usr=25 { tmp:2 = 0x2c9; export *[csreg]:4 tmp; } + +# Group 2 +UsrName: "pfmc0" is Group=2 & Usr=0 { tmp:2 = 0x200; export *[csreg]:4 tmp; } +UsrName: "pfmc1" is Group=2 & Usr=1 { tmp:2 = 0x201; export *[csreg]:4 tmp; } +UsrName: "pfmc2" is Group=2 & Usr=2 { tmp:2 = 0x202; export *[csreg]:4 tmp; } +UsrName: "pfm_ctl" is Group=2 & Usr=4 { tmp:2 = 0x208; export *[csreg]:4 tmp; } + + +:mfusr Rt, UsrName is $(I32) & $(ALU_2) & Rt & UsrName & $(ALU2Z) & Sub6=0b100000 { Rt = UsrName; } +:mfusr Rt, pc is $(I32) & $(ALU_2) & Rt & Group=0 & Usr=0b11111 & $(ALU2Z) & Sub6=0b100000 & pc { Rt = inst_next; } +:mtusr Rt, UsrName is $(I32) & $(ALU_2) & Rt & UsrName & $(ALU2Z) & Sub6=0b100001 { UsrName = Rt; } +:mtusr Rt, pc is $(I32) & $(ALU_2) & Rt & Group=0 & Usr=0b11111 & $(ALU2Z) & Sub6=0b100001 & pc { pc = Rt; goto[pc]; } # Not sure this works correctly + + +### Divide Instructions ### + +:div Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtlow & Dthigh & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101111 { Dtlow = Ra / Rb; Dthigh = Ra % Rb; } +:divs Dt, Ra, Rb is $(I32) & $(ALU_2) & Dtl=0 & Dt & Dtlow & Dthigh & Dtr=0 & Ra & Rb & $(ALU2Z) & Sub6=0b101110 { Dtlow = Ra s/ Rb; Dthigh = Ra s% Rb; } + + +### Load / Store Instruction (immediate) ### + +ByteOffset: off is Imm15s [ off = Imm15s << 0; ] { export *[const]:4 off; } +HalfOffset: off is Imm15s [ off = Imm15s << 1; ] { export *[const]:4 off; } +WordOffset: off is Imm15s [ off = Imm15s << 2; ] { export *[const]:4 off; } + +AddrByteRaImm15s: [Ra + ByteOffset] is Ra & ByteOffset { addr:4 = Ra + ByteOffset; export addr; } +AddrHalfRaImm15s: [Ra + HalfOffset] is Ra & HalfOffset { addr:4 = Ra + HalfOffset; export addr; } +AddrWordRaImm15s: [Ra + WordOffset] is Ra & WordOffset { addr:4 = Ra + WordOffset; export addr; } + +:lwi Rt, AddrWordRaImm15s is $(I32) & Opc=0b000010 & Rt & AddrWordRaImm15s { Rt = *AddrWordRaImm15s; } +:lhi Rt, AddrHalfRaImm15s is $(I32) & Opc=0b000001 & Rt & AddrHalfRaImm15s { local tmp:2 = *AddrHalfRaImm15s; Rt = zext(tmp); } +:lhsi Rt, AddrHalfRaImm15s is $(I32) & Opc=0b010001 & Rt & AddrHalfRaImm15s { local tmp:2 = *AddrHalfRaImm15s; Rt = sext(tmp); } +:lbi Rt, AddrByteRaImm15s is $(I32) & Opc=0b000000 & Rt & AddrByteRaImm15s { local tmp:1 = *AddrByteRaImm15s; Rt = zext(tmp); } +:lbsi Rt, AddrByteRaImm15s is $(I32) & Opc=0b010000 & Rt & AddrByteRaImm15s { local tmp:1 = *AddrByteRaImm15s; Rt = sext(tmp); } +:swi Rt, AddrWordRaImm15s is $(I32) & Opc=0b001010 & Rt & AddrWordRaImm15s { *AddrWordRaImm15s = Rt; } +:shi Rt, AddrHalfRaImm15s is $(I32) & Opc=0b001001 & Rt & AddrHalfRaImm15s { local tmp = Rt; *AddrHalfRaImm15s = tmp:2; } +:sbi Rt, AddrByteRaImm15s is $(I32) & Opc=0b001000 & Rt & AddrByteRaImm15s { local tmp = Rt; *AddrByteRaImm15s = tmp:1; } + +### Load / Store Instruction (immediate, postincr) ### + +:lwi.bi Rt, [Ra], WordOffset is $(I32) & Opc=0b000110 & Rt & Ra & WordOffset { Rt = *Ra; Ra = Ra + WordOffset; } +:lhi.bi Rt, [Ra], HalfOffset is $(I32) & Opc=0b000101 & Rt & Ra & HalfOffset { local tmp:2 = *Ra; Rt = zext(tmp); Ra = Ra + HalfOffset; } +:lhsi.bi Rt, [Ra], HalfOffset is $(I32) & Opc=0b010101 & Rt & Ra & HalfOffset { local tmp:2 = *Ra; Rt = sext(tmp); Ra = Ra + HalfOffset; } +:lbi.bi Rt, [Ra], ByteOffset is $(I32) & Opc=0b000100 & Rt & Ra & ByteOffset { local tmp:1 = *Ra; Rt = zext(tmp); Ra = Ra + ByteOffset; } +:lbsi.bi Rt, [Ra], ByteOffset is $(I32) & Opc=0b010100 & Rt & Ra & ByteOffset { local tmp:1 = *Ra; Rt = sext(tmp); Ra = Ra + ByteOffset; } +:swi.bi Rt, [Ra], WordOffset is $(I32) & Opc=0b001110 & Rt & Ra & WordOffset { *Ra = Rt; Ra = Ra + WordOffset; } +:shi.bi Rt, [Ra], HalfOffset is $(I32) & Opc=0b001101 & Rt & Ra & HalfOffset { local tmp = Rt; *Ra = tmp:2; Ra = Ra + HalfOffset; } +:sbi.bi Rt, [Ra], ByteOffset is $(I32) & Opc=0b001100 & Rt & Ra & ByteOffset { local tmp = Rt; *Ra = tmp:1; Ra = Ra + ByteOffset; } + + +### Load / Store Instruction (register) ### + +OffsetRbsv: (Rb "<<" sv) is Rb & sv { off:4 = Rb << sv; export off; } +AddrRaRbsv: [Ra + OffsetRbsv] is Ra & OffsetRbsv { addr:4 = Ra + OffsetRbsv; export addr; } + +:lw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00000010 { Rt = *AddrRaRbsv; } +:lh Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00000001 { local tmp:2 = *AddrRaRbsv; Rt = zext(tmp); } +:lhs Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00010001 { local tmp:2 = *AddrRaRbsv; Rt = sext(tmp); } +:lb Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00000000 { local tmp:1 = *AddrRaRbsv; Rt = zext(tmp); } +:lbs Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00010000 { local tmp:1 = *AddrRaRbsv; Rt = sext(tmp); } +:sw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00001010 { *AddrRaRbsv = Rt; } +:sh Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00001001 { local tmp = Rt; *AddrRaRbsv = tmp:2; } +:sb Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00001000 { local tmp = Rt; *AddrRaRbsv = tmp:1; } + + +### Load / Store Instruction (register, postincr) ### + +:lw.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00000110 { Rt = *Ra; Ra = Ra + OffsetRbsv; } +:lh.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00000101 { local tmp:2 = *Ra; Rt = zext(tmp); Ra = Ra + OffsetRbsv; } +:lhs.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00010101 { local tmp:2 = *Ra; Rt = sext(tmp); Ra = Ra + OffsetRbsv; } +:lb.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00000100 { local tmp:1 = *Ra; Rt = zext(tmp); Ra = Ra + OffsetRbsv; } +:lbs.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00010100 { local tmp:1 = *Ra; Rt = sext(tmp); Ra = Ra + OffsetRbsv; } +:sw.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00001110 { *Ra = Rt; Ra = Ra + OffsetRbsv; } +:sh.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00001101 { local tmp = Rt; *Ra = tmp:2; Ra = Ra + OffsetRbsv; } +:sb.bi Rt, [Ra], OffsetRbsv is $(I32) & $(MEM) & Rt & Ra & OffsetRbsv & Sub8=0b00001100 { local tmp = Rt; *Ra = tmp:1; Ra = Ra + OffsetRbsv; } + + +### Load / Store Multiple Word Instruction ### + + +@include "lsmw.sinc" + +LsmwBa_: "b" is LsmwBa=0 { } +LsmwBa_: "a" is LsmwBa=1 { } + +LsmwId_: "i" is LsmwId=0 { } +LsmwId_: "d" is LsmwId=1 { } + +LsmwM_: "" is LsmwRa & LsmwM=0 { } +LsmwM_: "m" is LsmwRa & LsmwM=1 { LsmwRa = mult_addr; } + + +:lmw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00) ... & Lmw.regs +{ + mult_addr = LsmwRa; + build Lmw.regs; + build LsmwM_; +} + +:smw.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b00) ... & Smw.regs +{ + mult_addr = LsmwRa; + build Smw.regs; + build LsmwM_; +} + + +### Load / Store Instruction for Atomic Updates ### + +:llw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00011000 { Rt = *AddrRaRbsv; } +:scw Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00011001 { *AddrRaRbsv = Rt; } + + +### Load / Store Instructions with User-mode Privilege ### + +# TODO : special constraint (user-mode address translation) + +:lwup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00100010 { Rt = *AddrRaRbsv; } +:swup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00101010 { *AddrRaRbsv = Rt; } + + +### Jump Instruction ### + +Rel24: addr is Imm24s [ addr = inst_start + (Imm24s << 1); ] { export *:4 addr; } + +:j Rel24 is $(I32) & $(JI) & JIt=0 & Rel24 { goto Rel24; } +:jal Rel24 is $(I32) & $(JI) & JIt=1 & Rel24 { lp = inst_next; call Rel24; } +:jr Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00000 { goto [Rb]; } +:ret Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=1 & Sub5=0b00000 { return [Rb]; } +:jral Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00001 { Rt = inst_next; call [Rb]; } + + +### Branch Instruction ### +Rel14: addr is Imm14s [ addr = inst_start + (Imm14s << 1); ] { export *:4 addr; } +Rel16: addr is Imm16s [ addr = inst_start + (Imm16s << 1); ] { export *:4 addr; } + +:beq Rt, Ra, Rel14 is $(I32) & $(BR1) & Rt & Ra & Br1t=0 & Rel14 { if(Rt == Ra) goto Rel14; } +:bne Rt, Ra, Rel14 is $(I32) & $(BR1) & Rt & Ra & Br1t=1 & Rel14 { if(Rt != Ra) goto Rel14; } +:beqz Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0010 & Rel16 { if(Rt == 0) goto Rel16; } +:bnez Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0011 & Rel16 { if(Rt != 0) goto Rel16; } +:bgez Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0100 & Rel16 { if(Rt s>= 0) goto Rel16; } +:bltz Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0101 & Rel16 { if(Rt s< 0) goto Rel16; } +:bgtz Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0110 & Rel16 { if(Rt s> 0) goto Rel16; } +:blez Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b0111 & Rel16 { if(Rt s<= 0) goto Rel16; } + + +### Branch with link Instruction ### + +:bgezal Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b1100 & Rel16 +{ + lp = inst_next; + if(Rt s>= 0) goto ; + call Rel16; + +} + +:bltzal Rt, Rel16 is $(I32) & $(BR2) & Rt & Br2t=0b1101 & Rel16 +{ + lp = inst_next; + if(Rt s< 0) goto ; + call Rel16; + +} + + +### Read / Write System Registers ### + +# TODO : special instruction, do we create the system registers ? +define pcodeop mfsr; +define pcodeop mtsr; + +csr: csr_reg is SrIdx [ csr_reg = $(CSR_REG_START) + SrIdx; ] { export *[csreg]:4 csr_reg; } + +:mfsr Rt, csr is $(I32) & $(MISC) & Rt & csr & Rd=0 & Sub5=0b00010 { Rt = csr; } +:mtsr Rt, csr is $(I32) & $(MISC) & Rt & csr & Rd=0 & Sub5=0b00011 { csr = Rt; } + + +### Jump Register with System Register Update ### + +# TODO : special constraint (address translation off) + +:jr.itoff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b01 & Jz=0 & JrHint=0 & Sub5=0b00000 { goto [Rb]; } +:jr.toff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b11 & Jz=0 & JrHint=0 & Sub5=0b00000 { goto [Rb]; } +:jral.iton Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b01 & Jz=0 & JrHint=0 & Sub5=0b00001 { Rt = inst_next; call [Rb]; } +:jral.ton Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b11 & Jz=0 & JrHint=0 & Sub5=0b00001 { Rt = inst_next; call [Rb]; } + + +### MMU Instruction ### + +define pcodeop TLB_TargetRead; +define pcodeop TLB_TargetWrite; +define pcodeop TLB_RWrite; +define pcodeop TLB_RWriteLock; +define pcodeop TLB_Unlock; +define pcodeop TLB_Probe; +define pcodeop TLB_Invalidate; +define pcodeop TLB_FlushAll; + +:tlbop Ra,"TargetRead" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=0 & Sub5=0b01110 { TLB_TargetRead(Ra:4); } +:tlbop Ra,"TargetWrite" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=1 & Sub5=0b01110 { TLB_TargetWrite(Ra:4); } +:tlbop Ra,"RWrite" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=2 & Sub5=0b01110 { TLB_RWrite(Ra:4); } +:tlbop Ra,"RWriteLock" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=3 & Sub5=0b01110 { TLB_RWriteLock(Ra:4); } +:tlbop Ra,"Unlock" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=4 & Sub5=0b01110 { TLB_Unlock(Ra:4); } +:tlbop Rt,Ra,"Probe" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=5 & Sub5=0b01110 { TLB_Probe(Rt:4, Ra:4); } +:tlbop Ra,"Invalidate" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=6 & Sub5=0b01110 { TLB_Invalidate(Ra:4); } +:tlbop "FlushAll" is $(I32) & $(MISC) & Rt & Ra & Rb=0 & TlbopSub=7 & Sub5=0b01110 { TLB_FlushAll(); } + + +### Conditional Move ### + +:cmovz Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11010 +{ + if(Rb != 0) goto ; + Rt = Ra; + +} + +:cmovn Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b11011 +{ + if(Rb == 0) goto ; + Rt = Ra; + +} + + +### Synchronization Instruction ### + +# TODO : special function, and subfunctions + +define pcodeop msync; +define pcodeop isync; + +:msync MsyncSub is $(I32) & $(MISC) & Rt=0 & MsyncZ=0 & MsyncSub & Sub5=0b01100 { msync(MsyncSub:1); } +:isync Rt is $(I32) & $(MISC) & Rt & Ra=0 & Rb=0 & Rd=0 & Sub5=0b01101 { isync(Rt:4); } + +### Prefetch Instruction ### + +define pcodeop dpref; + +OffsetRbsv2: (Rb "<<" sv) is Rb & sv { off:4 = Rb << (sv + 1); export off; } +AddrRaRbsv2: [Ra + OffsetRbsv2] is Ra & OffsetRbsv2 { addr:4 = Ra + OffsetRbsv2; export addr; } + +:dpref DprefSub, AddrRaRbsv2 is $(I32) & $(MEM) & DprefD=0 & DprefSub & AddrRaRbsv2 & Sub8=0b00010011 { + dpref(DprefSub:1, AddrRaRbsv2:4); +} + +DprefD_: "w" is DprefD=0 { } +DprefD_: "d" is DprefD=1 { } + +DprefiAddr: [Ra + Offset] is DprefD=0 & Ra & Imm15s [ Offset = Imm15s << 2; ] { export *[const]:4 Offset; } +DprefiAddr: [Ra + Offset] is DprefD=1 & Ra & Imm15s [ Offset = Imm15s << 3; ] { export *[const]:4 Offset; } + +:dprefi.^DprefD_ DprefSub, DprefiAddr is $(I32) & Opc=0b010011 & DprefD_ & DprefSub & DprefiAddr { + dpref(DprefSub:1, DprefiAddr:4); +} + + +### NOP Instruction ### + +:nop is $(I32) & $(ALU_1) & Rt=0 & Ra=0 & Imm5u=0 & Rd=0 & Sub5=0b01001 { } + + +### Serialization Instruction ### + +define pcodeop dsb; +define pcodeop isb; + +:dsb is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & Rd=0 & Sub5=0b01000 { dsb(); } +:isb is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & Rd=0 & Sub5=0b01001 { isb(); } + + +### Exception Generation Instruction ### + +define pcodeop break; +define pcodeop syscall; +define pcodeop trap; + +:break Swid is $(I32) & $(MISC) & Rt=0 & Swid & Sub5=0b01010 { break(Swid:4); } +:syscall Swid is $(I32) & $(MISC) & Rt=0 & Swid & Sub5=0b01011 { syscall(Swid:4); } +:trap Swid is $(I32) & $(MISC) & Rt=0 & Swid & Sub5=0b00101 { trap(Swid:4); } + +:teqz Rt, Swid is $(I32) & $(MISC) & Rt & Swid & Sub5=0b00110 +{ + if(Rt != 0) goto ; + trap(Swid:4); + +} + +:tnez Rt, Swid is $(I32) & $(MISC) & Rt & Swid & Sub5=0b00111 +{ + if(Rt == 0) goto ; + trap(Swid:4); + +} + + +### Special Return Instruction ### + +:iret is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & Rd=0 & Sub5=0b00100 { return [ipc]; } + +# TODO : special constraint (address translation off) +:ret.itoff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b01 & Jz=0 & JrHint=1 & Sub5=0b00000 { return [Rb]; } +:ret.toff Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b11 & Jz=0 & JrHint=1 & Sub5=0b00000 { return [Rb]; } + + +### Cache Control Instruction ### + +# TODO : special function, with subfunctions +define pcodeop cctl; + +:cctl Rt, Ra, CctlLevel, CctlSub is $(I32) & $(MISC) & Rt & Ra & CctlZ=0 & CctlLevel & CctlSub & Sub5=0b00001 { cctl(Rt:4, Ra:4, CctlLevel:1, CctlSub:1); } + + +# Miscellaneous Instructions (Baseline) + +# TODO : special function. Not sure if we use context or registers for this. + +define pcodeop setgie; + +SetgieEN: "d" is Toggle=0 { setgie(0:1); } +SetgieEN: "e" is Toggle=1 { setgie(1:1); } + +:setgie.^SetgieEN is $(I32) & $(MISC) & ToggleL=0 & SetgieEN & SrIdx=0b0010000000 & Rd=0b00010 & Sub5=0b00011 { } + +define pcodeop setend; + +SetendBE: "l" is Toggle=0 { setend(0:1); } +SetendBE: "b" is Toggle=1 { setend(1:1); } + +:setend.^SetendBE is $(I32) & $(MISC) & ToggleL=0 & SetendBE & SrIdx=0b0010000000 & Rd=0b00001 & Sub5=0b00011 { } + +:standby StandbySub is $(I32) & $(MISC) & Rt=0 & Ra=0 & Rb=0 & StandbyZ=0 & StandbySub & Sub5=0b00000 { goto inst_start; } + + + +### 32-bit Baseline V2 instructions ### + +### ALU Instructions ### + +:addi.gp is $(I32) & $(SBGP) & Rt & GpSub1=0b1 & Imm19s { Rt = gp + Imm19s; } + + +### Multiply and Divide Instructions (V2) ### + +:mulr64 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b101001 & Rtl & Rth +{ + res:8 = zext(Ra) * zext(Rb); + Rtl = res[32,32]; + Rth = res[0,32]; + +} + +:mulsr64 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b101000 & Rtl & Rth +{ + res:8 = sext(Ra) * sext(Rb); + Rtl = res[32,32]; + Rth = res[0,32]; +} + +:maddr32 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b110011 { Rt = Rt + (Ra * Rb); } +:msubr32 Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(GPR) & Sub6=0b110101 { Rt = Rt - (Ra * Rb); } +:divr Rt, Rs, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rs & Sub5=0b10111 { local div = Ra / Rb; local mod = Ra % Rb; Rs = mod; Rt = div; } +:divsr Rt, Rs, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rs & Sub5=0b10110 { local div = Ra s/ Rb; local mod = Ra s% Rb; Rs = mod; Rt = div; } + + +### Load/Store Instructions ### + +GpByteAddress: [+ off] is Imm19s [ off = Imm19s << 0; ] { addr:4 = gp + off; export addr; } +GpHalfAddress: [+ off] is Imm18s [ off = Imm18s << 1; ] { addr:4 = gp + off; export addr; } +GpWordAddress: [+ off] is Imm17s [ off = Imm17s << 2; ] { addr:4 = gp + off; export addr; } + +:lbi.gp Rt, GpByteAddress is $(I32) & $(LBGP) & Rt & GpSub1=0b0 & GpByteAddress { local tmp:1 = *GpByteAddress; Rt = zext(tmp); } +:lbsi.gp Rt, GpByteAddress is $(I32) & $(LBGP) & Rt & GpSub1=0b1 & GpByteAddress { local tmp:1 = *GpByteAddress; Rt = sext(tmp); } +:lhi.gp Rt, GpHalfAddress is $(I32) & $(HWGP) & Rt & GpSub2=0b00 & GpHalfAddress { local tmp:2 = *GpHalfAddress; Rt = zext(tmp); } +:lhsi.gp Rt, GpHalfAddress is $(I32) & $(HWGP) & Rt & GpSub2=0b01 & GpHalfAddress { local tmp:2 = *GpHalfAddress; Rt = sext(tmp); } +:lwi.gp Rt, GpWordAddress is $(I32) & $(HWGP) & Rt & GpSub3=0b110 & GpWordAddress { Rt = *GpWordAddress; } +:sbi.gp Rt, GpByteAddress is $(I32) & $(SBGP) & Rt & GpSub1=0b0 & GpByteAddress { local tmp = Rt; *GpByteAddress = tmp:1; } +:shi.gp Rt, GpHalfAddress is $(I32) & $(HWGP) & Rt & GpSub2=0b10 & GpHalfAddress { local tmp = Rt; *GpHalfAddress = tmp:2; } +:swi.gp Rt, GpWordAddress is $(I32) & $(HWGP) & Rt & GpSub3=0b111 & GpWordAddress { *GpWordAddress = Rt; } + + +:lmwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=0 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01) ... & Lmwa.regs +{ + mult_addr = LsmwRa; + build Lmwa.regs; + build LsmwM_; +} + +:smwa.^LsmwBa_^LsmwId_^LsmwM_ LsmwRb, [LsmwRa], LsmwRe, Enable4 is ($(I32) & $(LSMW) & LsmwRb & LsmwRa & LsmwRe & Enable4 & LsmwLs=1 & LsmwBa_ & LsmwId_ & LsmwM_ & LsmwSub=0b01) ... & Smwa.regs +{ + mult_addr = LsmwRa; + build Smwa.regs; + build LsmwM_; +} + +:lbup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00100000 { local tmp:1 = *AddrRaRbsv; Rt = zext(tmp); } +:sbup Rt, AddrRaRbsv is $(I32) & $(MEM) & Rt & AddrRaRbsv & Sub8=0b00101000 { local tmp = Rt; *AddrRaRbsv = tmp:1; } + + + +### 32-bit Baseline V3 instructions ### + +### ALU Instructions with Shift Operation (v3) ### + +:add_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00000 { Rt = Ra + (Rb << sh); } +:and_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00010 { Rt = Ra & (Rb << sh); } +:or_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00100 { Rt = Ra | (Rb << sh); } +:sub_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00001 { Rt = Ra - (Rb << sh); } +:xor_slli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b00011 { Rt = Ra ^ (Rb << sh); } + +:add_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11100 { Rt = Ra + (Rb << sh); } +:and_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11110 { Rt = Ra & (Rb << sh); } +:or_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b10101 { Rt = Ra | (Rb << sh); } +:sub_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11101 { Rt = Ra - (Rb << sh); } +:xor_srli Rt, Ra, Rb, sh is $(I32) & $(ALU_1) & Rt & Ra & Rb & sh & Sub5=0b11111 { Rt = Ra ^ (Rb << sh); } + +### Conditional Branch and Jump Instructions (V3) ### + +Rel8: addr is Imm8s [ addr = inst_start + (Imm8s << 1); ] { export *:4 addr; } +:beqc Rt, Imm11s, Rel8 is $(I32) & $(BR3) & Rt & Bxxc=0 & Imm11s & Rel8 { if(Rt == Imm11s) goto Rel8; } +:bnec Rt, Imm11s, Rel8 is $(I32) & $(BR3) & Rt & Bxxc=1 & Imm11s & Rel8 { if(Rt != Imm11s) goto Rel8; } + +:jralnez Rt,Rb is $(I32) & $(JREG) & Rt & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00011 { if(Rb == 0) goto ; Rt = inst_next; call [Rb]; } +:jrnez Rb is $(I32) & $(JREG) & Rt=0 & Ra=0 & Rb & DtIt=0b00 & Jz=0 & JrHint=0 & Sub5=0b00010 { if(Rb == 0) goto ; goto [Rb]; } + +### Bit Manipulation Instructions (V3) ### + +:bitc Rt, Ra, Rb is $(I32) & $(ALU_1) & Rt & Ra & Rb & Rd=0 & Sub5=0b10010 { Rt = Ra & (~Rb); } +:bitci Rt, Ra, Imm15u is $(I32) & Opc=0b110011 & Rt & Ra & Imm15u { Rt = Ra & (~Imm15u); } + +### Cache Control Instruction (V3) ### + +# TODO: Add CCTL L1D_WBALL, level + + +### 32-bit ISA extension ### + +### ALU Instruction (Performance) ### + + +:abs Rt, Ra is $(I32) & $(ALU_2) & Rt & Ra & Rb=0 & $(ALU2Z) & Sub6=0b000011 +{ + gez:4 = zext(Ra s>= 0); + ltz:4 = zext(Ra s< 0); + Rt = (Ra * gez) | ((-Ra) * ltz); +} + +:ave Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b000010 +{ + Rt = (Ra + Rb + 1) s>> 2; +} + +:max Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b000000 +{ + altb:4 = zext(Ra s< Rb); + ageb:4 = zext(Ra s>= Rb); + Rt = (Ra * ageb) | (Rb * altb); +} + +:min Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b000001 +{ + altb:4 = zext(Ra s< Rb); + ageb:4 = zext(Ra s>= Rb); + Rt = (Ra * altb) | (Rb * ageb); +} + +:bset Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001000 { Rt = Ra | (1 << Imm5u); } +:bclr Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001001 { Rt = Ra & ~(1 << Imm5u); } +:btgl Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001010 { Rt = Ra ^ (1 << Imm5u); } +:btst Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b001011 { Rt = (Ra >> Imm5u) & 1; } + +:clips Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b000100 +{ + local upper:4 = (1 << Imm5u) - 1; + local lower:4 = -(1 << Imm5u); + if(Ra s<= upper) goto ; + Rt = upper; + goto ; + + if(Ra s>= lower) goto ; + Rt = lower; + goto ; + + Rt = Ra; + +} +:clip Rt, Ra, Imm5u is $(I32) & $(ALU_2) & Rt & Ra & Imm5u & $(ALU2Z) & Sub6=0b000101 +{ + local upper:4 = (1 << Imm5u) - 1; + if(Ra s<= upper) goto ; + Rt = upper; + goto ; + + if(Ra s>= 0) goto ; + Rt = 0; + goto ; + + Rt = Ra; + +} + +:clz Rt, Ra is $(I32) & $(ALU_2) & Rt & Ra & Imm5u=0 & $(ALU2Z) & Sub6=0b000111 +{ + countTmp:4 = 0; + inputTmp:4 = Ra; + + + if ((inputTmp & 0x80000000) != 0) goto ; + + countTmp = countTmp + 1; + inputTmp = (inputTmp << 1) | 1; + goto ; + + + Rt = countTmp; +} + +:clo Rt, Ra is $(I32) & $(ALU_2) & Rt & Ra & Imm5u=0 & $(ALU2Z) & Sub6=0b000110 +{ + countTmp:4 = 0; + inputTmp:4 = Ra; + + + if ((inputTmp & 0x80000000) == 0) goto ; + + countTmp = countTmp + 1; + inputTmp = (inputTmp << 1) | 1; + goto ; + + + Rt = countTmp; +} + + +### Performance Extension V2 ### + + +# TODO : arithmetic functions: bs* +:bse is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b001100 unimpl +:bsp is $(I32) & $(ALU_2) & Rt & Ra & Rb & $(ALU2Z) & Sub6=0b001101 unimpl + +macro add_abs_diff(dst, src1, src2, shift) +{ + local src1_ = src1 >> shift; + local src2_ = src2 >> shift; + local src1__ = src1_:1; + local src2__ = src2_:1; + local a:1 = src1__ - src2__; + local agez:1 = zext(a s>= 0); + local altz:1 = zext(a s< 0); + local aabs:1 = (a * agez) | ((-a) * altz); + dst = dst + zext(aabs); +} +:pbsad Rt, Ra, Rb is $(I32) & $(SIMD) & Rt & Ra & Rb & Rd=0 & Sub5=0b0000 +{ + Rt = 0; + add_abs_diff(Rt, Ra, Rb, 0); + add_abs_diff(Rt, Ra, Rb, 8); + add_abs_diff(Rt, Ra, Rb, 16); + add_abs_diff(Rt, Ra, Rb, 24); +} +:pbsada Rt, Ra, Rb is $(I32) & $(SIMD) & Rt & Ra & Rb & Rd=0 & Sub5=0b0001 +{ + add_abs_diff(Rt, Ra, Rb, 0); + add_abs_diff(Rt, Ra, Rb, 8); + add_abs_diff(Rt, Ra, Rb, 16); + add_abs_diff(Rt, Ra, Rb, 24); +} + + +# 32-bit String Extension +:ffb Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b0001110 { + match:1 = Rb[0,8]; + m1:1 = (Ra[0,8] == match); + m2:1 = (Ra[8,8] == match); + m3:1 = (Ra[16,8] == match); + m4:1 = (Ra[24,8] == match); + Rt = -4; + if (m1) goto inst_next; + Rt = -3; + if (m2) goto inst_next; + Rt = -2; + if (m3) goto inst_next; + Rt = -1; + if (m4) goto inst_next; + Rt = 0; + # choosery method + # rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1); +} + +:ffbi Rt, Ra, Imm8u is $(I32) & $(ALU_2) & Rt & Ra & Imm8u & Sub7=0b1001110 { + match:1 = Imm8u; + m1:1 = (Ra[0,8] == match); + m2:1 = (Ra[8,8] == match); + m3:1 = (Ra[16,8] == match); + m4:1 = (Ra[24,8] == match); + Rt = -4; + if (m1) goto inst_next; + Rt = -3; + if (m2) goto inst_next; + Rt = -2; + if (m3) goto inst_next; + Rt = -1; + if (m4) goto inst_next; + Rt = 0; +} + +:ffmism Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b0001111 { + match:1 = Rb[0,8]; + m1:1 = (Ra[0,8] != Rb[0,8]); + m2:1 = (Ra[8,8] != Rb[8,8]); + m3:1 = (Ra[16,8] != Rb[16,8]); + m4:1 = (Ra[24,8] != Rb[24,8]); +@if ENDIAN == "little" + Rt = -4; + if (m1) goto inst_next; + Rt = -3; + if (m2) goto inst_next; + Rt = -2; + if (m3) goto inst_next; + Rt = -1; + if (m4) goto inst_next; + Rt = 0; + # choosery method + # rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1); +@else + Rt = -4; + if (m4) goto inst_next; + Rt = -3; + if (m3) goto inst_next; + Rt = -2; + if (m2) goto inst_next; + Rt = -1; + if (m1) goto inst_next; + Rt = 0; +@endif +} + +:flmism Rt, Ra, Rb is $(I32) & $(ALU_2) & Rt & Ra & Rb & Sub3=0 & Sub7=0b1001111 { + match:1 = Rb[0,8]; + m1:1 = (Ra[0,8] != Rb[0,8]); + m2:1 = (Ra[8,8] != Rb[8,8]); + m3:1 = (Ra[16,8] != Rb[16,8]); + m4:1 = (Ra[24,8] != Rb[24,8]); +@if ENDIAN == "little" + Rt = -1; + if (m4) goto inst_next; + Rt = -2; + if (m3) goto inst_next; + Rt = -3; + if (m2) goto inst_next; + Rt = -4; + if (m1) goto inst_next; + Rt = 0; + # choosery method + # rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1); +@else + Rt = -1; + if (m1) goto inst_next; + Rt = -2; + if (m2) goto inst_next; + Rt = -3; + if (m3) goto inst_next; + Rt = -4; + if (m4) goto inst_next; + Rt = 0; +@endif +} + +########### 16b ############ + +define token instr16(16) + opsz = (15, 15) + opc4 = (11, 14) + opc5 = (10, 14) + opc6 = (9, 14) + opc7 = (8, 14) + opc8 = (7, 14) + opc10 = (5, 14) + re2 = (5, 6) + rt5 = (5, 9) + ra4 = (5, 8) + rt4 = (5, 8) + ra5 = (0, 4) + rb5 = (0, 4) + rt5b = (0, 4) + rt3 = (6, 8) + rt3b = (8, 10) + ra3 = (3, 5) + rb3 = (0, 2) + bit5 = (5,5) + bit6 = (6,6) + bit7 = (7,7) + bit8 = (8,8) + imm3u = (0, 2) + imm3ub = (3, 5) + imm4u = (5, 8) + imm5u = (0, 4) + imm5s = (0, 4) signed + imm6u = (0, 5) + imm7u = (0, 6) + imm8s = (0, 7) signed + imm10s = (0, 9) signed + xwi37_ls = (7, 7) + swid9 = (0, 8) + rt5e1 = (4, 7) + rt5e2 = (4, 7) + ra5e1 = (0, 3) + ra5e2 = (0, 3) +; + +attach variables [rt5 ra5 rb5 rt5b] [ + a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 s6 s7 s8 ta t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 p0 p1 fp gp lp sp +]; + +attach variables [ra4 rt4] [ + a0 a1 a2 a3 a4 a5 s0 s1 s2 s3 s4 s5 t0 t1 t2 t3 +]; + +attach variables [rt3 ra3 rt3b rb3] [ + a0 a1 a2 a3 a4 a5 s0 s1 +]; + +attach variables [ra5e1 rt5e1] [ + a0 a2 a4 s0 s2 s4 s6 s8 t0 t2 t4 t6 t8 p0 fp lp +]; +attach variables [ra5e2 rt5e2] [ + a1 a3 a5 s1 s3 s5 s7 ta t1 t3 t5 t7 t9 p1 gp sp +]; + +attach variables [re2] [ + s0 s2 s4 s8 +]; + + +@define I16 "(opsz=1)" +@define BFMI333 "(opc6=0b001011)" +@define XWI37 "(opc4=0b0111)" +@define XWI37SP "(opc4=0b1110)" +@define MISC33 "(opc6=0b111111)" + + +### Move Instruction ### + +:movi55 rt5, imm5s is $(I16) & opc5=0b00001 & rt5 & imm5s { rt5 = imm5s; } +:mov55 rt5, ra5 is $(I16) & opc5=0b00000 & rt5 & ra5 { rt5 = ra5; } + + +### Add/Sub Instruction with Immediate ### + +:addi45 rt4, imm5u is $(I16) & opc6=0b000110 & rt4 & imm5u { rt4 = rt4 + imm5u; } +:addi333 rt3, ra3, imm3u is $(I16) & opc6=0b001110 & rt3 & ra3 & imm3u { rt3 = ra3 + imm3u; } +:subi45 rt4, imm5u is $(I16) & opc6=0b000111 & rt4 & imm5u { rt4 = rt4 - imm5u; } +:subi333 rt3, ra3, imm3u is $(I16) & opc6=0b001111 & rt3 & ra3 & imm3u { rt3 = ra3 - imm3u; } + + +### Add/Sub Instruction ### + +:add45 rt4, rb5 is $(I16) & opc6=0b000100 & rt4 & rb5 { rt4 = rt4 + rb5; } +:add333 rt3, ra3, rb3 is $(I16) & opc6=0b001100 & rt3 & ra3 & rb3 { rt3 = ra3 + rb3; } +:sub45 rt4, rb5 is $(I16) & opc6=0b000101 & rt4 & rb5 { rt4 = rt4 - rb5; } +:sub333 rt3, ra3, rb3 is $(I16) & opc6=0b001101 & rt3 & ra3 & rb3 { rt3 = ra3 - rb3; } + + +### Shift Instruction with Immediate ### + +:srai45 rt4, imm5u is $(I16) & opc6=0b001000 & rt4 & imm5u { rt4 = rt4 s>> imm5u; } +:srli45 rt4, imm5u is $(I16) & opc6=0b001001 & rt4 & imm5u { rt4 = rt4 >> imm5u; } +:slli333 rt3, ra3, imm3u is $(I16) & opc6=0b001010 & rt3 & ra3 & imm3u { rt3 = ra3 << imm3u; } + + +### Bit Field Mask Instruction with Immediate ### + +:zeb33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b000 { local tmp = ra3; rt3 = zext(tmp:1); } +:zeh33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b001 { local tmp = ra3; rt3 = zext(tmp:2); } +:seb33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b010 { local tmp = ra3; rt3 = sext(tmp:1); } +:seh33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b011 { local tmp = ra3; rt3 = sext(tmp:2); } +:xlsb33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b100 { rt3 = ra3 & 1; } +:x11b33 rt3, ra3 is $(I16) & $(BFMI333) & rt3 & ra3 & imm3u=0b101 { rt3 = ra3 & 0x7ff; } + + +### Load / Store Instruction ### + +:lwi450 rt4,[ra5] is $(I16) & opc6=0b011010 & rt4 & ra5 { rt4 = *ra5; } + +rel3w: off is imm3u [ off = imm3u << 2; ] { export *[const]:4 off; } +rel3h: off is imm3u [ off = imm3u << 1; ] { export *[const]:4 off; } +rel3b: off is imm3u [ off = imm3u << 0 ; ] { export *[const]:4 off; } +ra3_rel3w: [ra3 + rel3w] is ra3 & rel3w { addr:4 = ra3 + rel3w; export addr; } +ra3_rel3h: [ra3 + rel3h] is ra3 & rel3h { addr:4 = ra3 + rel3h; export addr; } +ra3_rel3b: [ra3 + rel3b] is ra3 & rel3b { addr:4 = ra3 + rel3b; export addr; } + +:lwi333 rt3, ra3_rel3w is $(I16) & opc6=0b010000 & rt3 & ra3_rel3w { rt3 = *ra3_rel3w; } +:lwi333.bi rt3, [ra3], rel3w is $(I16) & opc6=0b010001 & rt3 & ra3 & rel3w { rt3 = *ra3; ra3 = ra3 + rel3w; } +:lhi333 rt3, ra3_rel3h is $(I16) & opc6=0b010010 & rt3 & ra3_rel3h { local tmp:2 = *ra3_rel3h; rt3 = zext(tmp); } +:lbi333 rt3, ra3_rel3b is $(I16) & opc6=0b010011 & rt3 & ra3_rel3b { local tmp:1 = *ra3_rel3b; rt3 = zext(tmp); } +:swi450 rt4, [ra5] is $(I16) & opc6=0b011011 & rt4 & ra5 { *ra5 = rt4; } +:swi333 rt3, ra3_rel3w is $(I16) & opc6=0b010100 & rt3 & ra3_rel3w { *ra3_rel3w = rt3; } +:swi333.bi rt3, [ra3], rel3w is $(I16) & opc6=0b010101 & rt3 & ra3 & rel3w { *ra3 = rt3; ra3 = ra3 + rel3w; } +:shi333 rt3, ra3_rel3h is $(I16) & opc6=0b010110 & rt3 & ra3_rel3h { local tmp = rt3; *ra3_rel3h = tmp:2; } +:sbi333 rt3, ra3_rel3b is $(I16) & opc6=0b010111 & rt3 & ra3_rel3b { local tmp = rt3; *ra3_rel3b = tmp:1; } + + +### Load/Store Instruction with Implied FP ### + +rel7w: off is imm7u [ off = imm7u << 2; ] { export *[const]:4 off; } +fp_rel7w: [fp + rel7w] is fp & rel7w { addr:4 = fp + rel7w; export addr; } + +:lwi37 rt3b, fp_rel7w is $(I16) & rt3b & $(XWI37) & xwi37_ls=0 & fp_rel7w { rt3b = *fp_rel7w; } +:swi37 rt3b, fp_rel7w is $(I16) & rt3b & $(XWI37) & xwi37_ls=1 & fp_rel7w { *fp_rel7w = rt3b; } + + +### Branch and Jump Instruction ### + +rel8: addr is imm8s [ addr = inst_start + (imm8s << 1); ] { export *:4 addr; } + + +:beqs38 rt3b,rel8 is $(I16) & opc4=0b1010 & rt3b & rel8 { if(a5 == rt3b) goto rel8; } +:bnes38 rt3b,rel8 is $(I16) & opc4=0b1011 & rt3b & rel8 { if(a5 != rt3b) goto rel8; } +:beqz38 rt3b,rel8 is $(I16) & opc4=0b1000 & rt3b & rel8 { if(rt3b == 0) goto rel8; } +:bnez38 rt3b,rel8 is $(I16) & opc4=0b1001 & rt3b & rel8 { if(rt3b != 0) goto rel8; } + +:j8 rel8 is $(I16) & opc7=0b1010101 & rel8 { goto rel8; } +:jr5 rb5 is $(I16) & opc10=0b1011101000 & rb5 { goto [rb5]; } +:ret5 rb5 is $(I16) & opc10=0b1011101100 & rb5 { return [rb5]; } +:jral5 rb5 is $(I16) & opc10=0b1011101001 & rb5 { lp = inst_next; call [rb5]; } + + +### Compare and Branch Instruction ### + +:slti45 ra4, imm5u is $(I16) & opc6=0b110011 & ra4 & imm5u { ta = zext(ra4 < imm5u); } +:sltsi45 ra4, imm5u is $(I16) & opc6=0b110010 & ra4 & imm5u { ta = zext(ra4 s< imm5u); } +:slt45 ra4, rb5 is $(I16) & opc6=0b110001 & ra4 & rb5 { ta = zext(ra4 < rb5); } +:slts45 ra4, rb5 is $(I16) & opc6=0b110000 & ra4 & rb5 { ta = zext(ra4 s< rb5); } + +:beqzs8 rel8 is $(I16) & opc7=0b1101000 & rel8 { if(ta == 0) goto rel8; } +:bnezs8 rel8 is $(I16) & opc7=0b1101001 & rel8 { if(ta != 0) goto rel8; } + + +### Misc Instruction ### + +# V3 doesn't allow break16 with SWID greater than 31 +:break16 swid9 is $(I16) & opc6=0b110101 & imm4u=0 & swid9 { break(swid9:4); } +:nop16 is $(I16) & opc6=0b001001 & rt4=0 & imm5u=0 { } + + +### ALU Instructions (V2) ### + +:addi10.sp imm10s is $(I16) & opc5=0b11011 & imm10s { sp = sp + imm10s; } + + +### Load/Store Instruction (V2) ### + +sp_rel7w: [+ rel7w] is rel7w { addr:4 = sp + rel7w; export addr; } + +:lwi37.sp rt3b, sp_rel7w is $(I16) & rt3b & $(XWI37SP) & xwi37_ls=0 & sp_rel7w { rt3b = *sp_rel7w; } +:swi37.sp rt3b, sp_rel7w is $(I16) & rt3b & $(XWI37SP) & xwi37_ls=1 & sp_rel7w { *sp_rel7w = rt3b; } + + + +### 16-bit Baseline V3 instructions ### + +### ALU Instructions (V3 16-bit) ### + +imm6u_: imm8 is imm6u [ imm8 = imm6u << 2; ] { export *[const]:4 imm8; } +:addri36.sp rt3, imm6u_ is $(I16) & opc6=0b011000 & rt3 & imm6u_ { rt3 = sp + imm6u_; } +:add5.pc rt5b is $(I16) & opc10=0b1011101101 & rt5b { rt5b = pc + rt5b; } +:and33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b110 { rt3 = rt3 & ra3; } +:neg33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b010 { rt3 = -ra3; } +:not33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b011 { rt3 = ~ra3; } +:or33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b111 { rt3 = rt3 | ra3; } +:xor33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b101 { rt3 = rt3 ^ ra3; } + +### Bit Manipulation Instructions (V3 16-bit) ### + +:bmski33 rt3, imm3ub is $(I16) & opc6=0b001011 & rt3 & imm3ub & imm3u=0b110 { rt3 = (rt3 >> imm3ub) & 1; } +:fexti33 rt3, imm3ub is $(I16) & opc6=0b001011 & rt3 & imm3ub & imm3u=0b111 { rt3 = rt3 & ((1 << (imm3ub + 1)) - 1); } + +### Misc. Instructions (V3 16-bit) ### + +imm7n: off is imm5u [ off = -((32 - imm5u) << 2); ] { export *[const]:4 off; } +:lwi45.fe rt4, [imm7n] is $(I16) & opc6=0b011001 & rt4 & imm7n { addr:4 = s2 + imm7n; rt4 = *addr; } + +:movd44 rt5e1, ra5e1 is $(I16) & opc7=0b1111101 & rt5e1 & rt5e2 & ra5e1 & ra5e2 { rt5e1 = ra5e1; rt5e2 = ra5e2; } + +imm5u_: imm6 is imm5u [ imm6 = imm5u + 16; ] { export *[const]:4 imm6; } +:movpi45 rt4, imm5u_ is $(I16) & opc6=0b111101 & rt4 & imm5u_ { rt4 = imm5u_; } + +:mul33 rt3, ra3 is $(I16) & $(MISC33) & rt3 & ra3 & imm3u=0b100 { rt3 = rt3 * ra3; } + +# Note: POP25 and PUSH25 are highly untested ! And they just look messy :/ +imm5u__: imm8 is imm5u [ imm8 = imm5u << 3; ] { export *[const]:4 imm8; } + +macro push25_special() { Smwad(lp); Smwad(gp); Smwad(fp); } +macro push25_s0() { Smwad(s0); } +macro push25_s2() { Smwad(s2); Smwad(s1); push25_s0(); } +macro push25_s4() { Smwad(s4); Smwad(s3); push25_s2(); } +macro push25_s8() { Smwad(s8); Smwad(s7); Smwad(s6); Smwad(s5); push25_s4(); } + +push25_re: re2 is re2 & re2=0 { push25_s0(); } +push25_re: re2 is re2 & re2=1 { push25_s2(); } +push25_re: re2 is re2 & re2=2 { push25_s4(); } +push25_re: re2 is re2 & re2=3 { push25_s8(); } + +:push25 push25_re, imm5u__ is $(I16) & opc8=0b11111000 & re2 & push25_re & imm5u__ { + mult_addr = sp; + push25_special(); + build push25_re; + sp = mult_addr - imm5u__; + if(re2 < 1) goto ; + s2 = pc & 0xfffffffc; + +} + +macro pop25_special() { LmwOp(fp); LmwOp(gp); LmwOp(lp); } +macro pop25_s0() { LmwOp(s0); } +macro pop25_s2() { pop25_s0(); LmwOp(s1); LmwOp(s2); } +macro pop25_s4() { pop25_s2(); LmwOp(s3); LmwOp(s4); } +macro pop25_s8() { pop25_s4(); LmwOp(s5); LmwOp(s6); LmwOp(s7); LmwOp(s8); } + +pop25_re: re2 is re2 & re2=0 { pop25_s0(); } +pop25_re: re2 is re2 & re2=1 { pop25_s2(); } +pop25_re: re2 is re2 & re2=2 { pop25_s4(); } +pop25_re: re2 is re2 & re2=3 { pop25_s8(); } + +:pop25 pop25_re, imm5u__ is $(I16) & opc8=0b11111001 & re2 & pop25_re & imm5u__ { + mult_addr = sp; + build pop25_re; + pop25_special(); + sp = mult_addr + imm5u__; + return [lp]; +} + + +# EX9.IT + +imm9u_: imm9 is imm5u & imm4u [ imm9 = (imm4u << 5) | imm5u; ] { export *[const]:4 imm9; } +define pcodeop ex9; + +# TODO: Depending on the value of ITB.HW the address is either set by hardware or set by ITB.Addr +:ex9.it imm9u_ is $(I16) & opc6=0b110101 & (bit5=1 | bit6=1 | bit7=1 | bit8=1) & imm9u_ { + ex9(imm9u_); +} + +:ex9.it imm5u is $(I16) & opc10=0b1011101010 & imm5u { + ex9(imm5u:4); +} + + +########################## +# Floating Point Extension + +# FPU_FS1 +define pcodeop fadds; +:fadds Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x0 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fadds(Fsa, Fsb); +} + +define pcodeop fsubs; +:fsubs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x1 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fsubs(Fsa, Fsb); +} + +define pcodeop fcpynss; +:fcpynss Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x2 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fcpynss(Fsa, Fsb); +} + +define pcodeop fcpyss; +:fcpyss Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x3 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fcpyss(Fsa, Fsb); +} + +define pcodeop fmadds; +:fmadds Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x4 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fmadds(Fsa, Fsb); +} + +define pcodeop fmsubs; +:fmsubs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x5 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fmsubs(Fsa, Fsb); +} + +define pcodeop fcmovns; +:fcmovns Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x6 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fcmovns(Fsa, Fsb); +} + +define pcodeop fcmovzs; +:fcmovzs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x7 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fcmovzs(Fsa, Fsb); +} + +define pcodeop fnmadds; +:fnmadds Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x8 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fnmadds(Fsa, Fsb); +} + +define pcodeop fnmsubs; +:fnmsubs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0x9 & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fnmsubs(Fsa, Fsb); +} + +define pcodeop fmuls; +:fmuls Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xa & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fmuls(Fsa, Fsb); +} + +define pcodeop fdivs; +:fdivs Fst, Fsa, Fsb is $(I32) & $(COP) & fop4=0xb & Fst & Fsa & Fsb & cop4=0x0 { + Fst = fdivs(Fsa, Fsb); +} + +# FPU_FS1_F2OP + +define pcodeop fs2d; +:fs2d Fdt, Fsa is $(I32) & $(COP) & fop4=0xf & Fdt & Fsa & f2op=0 & cop4=0x0 { + Fdt = fs2d(Fsa); +} + +define pcodeop fsqrts; +:fsqrts Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=1 & cop4=0x0 { + Fst = fsqrts(Fsa); +} + +define pcodeop fabss; +:fabss Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x5 & cop4=0x0 { + Fst = fabss(Fsa); +} + +define pcodeop fui2s; +:fui2s Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x8 & cop4=0x0 { + Fst = fui2s(Fsa); +} + +define pcodeop fsi2s; +:fsi2s Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0xc & cop4=0x0 { + Fst = fsi2s(Fsa); +} + +define pcodeop fs2ui; +:fs2ui Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x10 & cop4=0x0 { + Fst = fs2ui(Fsa); +} + +define pcodeop fs2ui.z; +:fs2ui.z Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x14 & cop4=0x0 { + Fst = fs2ui.z(Fsa); +} + +define pcodeop fs2si; +:fs2si Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x18 & cop4=0x0 { + Fst = fs2si(Fsa); +} + +define pcodeop fs2si.z; +:fs2si.z Fst, Fsa is $(I32) & $(COP) & fop4=0xf & Fst & Fsa & f2op=0x1c & cop4=0x0 { + Fst = fs2si.z(Fsa); +} + +# FPU_FS2 +fcond: "eq" is fcnd=0 { local tmp:1 = 0; export *[const]:1 tmp; } +fcond: "lt" is fcnd=1 { local tmp:1 = 1; export *[const]:1 tmp; } +fcond: "le" is fcnd=2 { local tmp:1 = 2; export *[const]:1 tmp; } +fcond: "un" is fcnd=3 { local tmp:1 = 3; export *[const]:1 tmp; } + +fcmpe: "" is cmpe=0 { local tmp:1 = 0; export *[const]:1 tmp; } +fcmpe: ".e" is cmpe=1 { local tmp:1 = 1; export *[const]:1 tmp; } +define pcodeop fcmps; +:fcmp^fcond^"s"^fcmpe Fst, Fsa, Fsb is $(I32) & $(COP) & Fst & Fsa & Fsb & cop4=0x4 & fcond & fcmpe { + Fst = fcmps(Fsa, Fsb, fcond, fcmpe); +} + +# FPU_FD1 + +define pcodeop faddd; +:faddd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x0 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = faddd(Fda, Fdb); +} + +define pcodeop fsubd; +:fsubd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x1 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fsubd(Fda, Fdb); +} + +define pcodeop fcpynsd; +:fcpynsd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x2 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fcpynsd(Fda, Fdb); +} + +define pcodeop fcpysd; +:fcpysd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x3 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fcpysd(Fda, Fdb); +} + +define pcodeop fmaddd; +:fmaddd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x4 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fmaddd(Fda, Fdb); +} + +define pcodeop fmsubd; +:fmsubd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x5 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fmsubd(Fda, Fdb); +} + +define pcodeop fcmovnd; +:fcmovnd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x6 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fcmovnd(Fda, Fdb); +} + +define pcodeop fcmovzd; +:fcmovzd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x7 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fcmovzd(Fda, Fdb); +} + +define pcodeop fnmaddd; +:fnmaddd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x8 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fnmaddd(Fda, Fdb); +} + +define pcodeop fnmsubd; +:fnmsubd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0x9 & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fnmsubd(Fda, Fdb); +} + +define pcodeop fmuld; +:fmuld Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xa & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fmuld(Fda, Fdb); +} + +define pcodeop fdivd; +:fdivd Fdt, Fda, Fdb is $(I32) & $(COP) & fop4=0xb & Fdt & Fda & Fdb & cop4=0x8 { + Fdt = fdivd(Fda, Fdb); +} + +# FPU_FD1_F2OP +define pcodeop fd2s; +:fd2s Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0 & cop4=0x8 { + Fst = fd2s(Fda); +} + +define pcodeop fsqrtd; +:fsqrtd Fdt, Fda is $(I32) & $(COP) & fop4=0xf & Fdt & Fda & f2op=1 & cop4=0x8 { + Fdt = fsqrtd(Fda); +} + +define pcodeop fabsd; +:fabsd Fdt, Fda is $(I32) & $(COP) & fop4=0xf & Fdt & Fda & f2op=0x5 & cop4=0x8 { + Fdt = fabsd(Fda); +} + +define pcodeop fui2d; +:fui2d Fdt, Fsa is $(I32) & $(COP) & fop4=0xf & Fdt & Fsa & f2op=0x8 & cop4=0x8 { + Fdt = fui2d(Fsa); +} + +define pcodeop fsi2d; +:fsi2d Fdt, Fsa is $(I32) & $(COP) & fop4=0xf & Fdt & Fsa & f2op=0xc & cop4=0x8 { + Fdt = fsi2d(Fsa); +} + +define pcodeop fd2ui; +:fd2ui Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x10 & cop4=0x8 { + Fst = fd2ui(Fda); +} + +define pcodeop fd2ui.z; +:fd2ui.z Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x14 & cop4=0x8 { + Fst = fs2ui.z(Fda); +} + +define pcodeop fd2si; +:fd2si Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x18 & cop4=0x8 { + Fst = fd2si(Fda); +} + +define pcodeop fd2si.z; +:fd2si.z Fst, Fda is $(I32) & $(COP) & fop4=0xf & Fst & Fda & f2op=0x1c & cop4=0x8 { + Fst = fs2si.z(Fda); +} + +# FPU_FS2 +define pcodeop fcmpd; +:fcmp^fcond^"d"^fcmpe Fst, Fda, Fdb is $(I32) & $(COP) & Fst & Fda & Fdb & cop4=0xc & fcond & fcmpe { + Fst = fcmpd(Fda, Fdb, fcond, fcmpe); +} + +# FPU_MFCP +define pcodeop fmfsr; +:fmfsr Rt, Fsa is $(I32) & $(COP) & fop4=0x0 & Rt & Fsa & f2op=0x0 & cop4=0x1 { + Rt = fmfsr(Fsa); +} + +define pcodeop fmfdr; +:fmfdr Rt, Fda is $(I32) & $(COP) & fop4=0x1 & Rt & Fda & f2op=0x0 & cop4=0x1 { + Rt = fmfdr(Fda); +} + +# FPU_MTCP +define pcodeop fmtsr; +:fmtsr Rt, Fsa is $(I32) & $(COP) & fop4=0x0 & Rt & Fsa & f2op=0x0 & cop4=0x9 { + Fsa = fmtsr(Rt); +} + +define pcodeop fmtdr; +:fmtdr Rt, Fda is $(I32) & $(COP) & fop4=0x1 & Rt & Fda & f2op=0x0 & cop4=0x9 { + Fda = fmtdr(Rt); +} + +# FPU_FLS + +:fls Fst, AddrRaRbsv is $(I32) & $(COP) & Fst & AddrRaRbsv & fbi=0 & cop4=0x2 { + Fst = *AddrRaRbsv; +} + +:fls.bi Fst [Ra], OffsetRbsv is $(I32) & $(COP) & Fst & Ra & OffsetRbsv & fbi=1 & cop4=2 { + Fst = *Ra; + Ra = Ra + OffsetRbsv; +} + +# FPU_FLD + +:fld Fdt, AddrRaRbsv is $(I32) & $(COP) & Fdt & AddrRaRbsv & fbi=0 & cop4=0x3 { + Fdt = *AddrRaRbsv; +} + +:fld.bi Fdt [Ra], OffsetRbsv is $(I32) & $(COP) & Fdt & Ra & OffsetRbsv & fbi=1 & cop4=3 { + Fdt = *Ra; + Ra = Ra + OffsetRbsv; +} + +# FPU_FSS + +:fss Fst, AddrRaRbsv is $(I32) & $(COP) & Fst & AddrRaRbsv & fbi=0 & cop4=0xa { + *AddrRaRbsv = Fst; +} + +:fss.bi Fst [Ra], OffsetRbsv is $(I32) & $(COP) & Fst & Ra & OffsetRbsv & fbi=1 & cop4=0xa { + *Ra = Fst; + Ra = Ra + OffsetRbsv; +} + +# FPU_FSD +:fsd Fdt, AddrRaRbsv is $(I32) & $(COP) & Fdt & AddrRaRbsv & fbi=0 & cop4=0xb { + *AddrRaRbsv = Fdt; +} + +:fsd.bi Fdt [Ra], OffsetRbsv is $(I32) & $(COP) & Fdt & Ra & OffsetRbsv & fbi=1 & cop4=0xb { + *Ra = Fdt; + Ra = Ra + OffsetRbsv; +} + + +# LWC0 +AddrRaImm12s: [Ra + offs] is Ra & Imm12s [ offs = Imm12s << 2; ] { addr:4 = Ra + offs; export addr; } +OffImm12s: (offs) is Imm12s [ offs = Imm12s << 2; ] { export *[const]:4 offs; } + +:flsi Fst, AddrRaImm12s is $(I32) & $(LWC) & Fst & cpn=0 & fsbi=0 & AddrRaImm12s { + Fst = *AddrRaImm12s; +} + +:flsi.bi Fst [Ra], OffImm12s is $(I32) & $(LWC) & Fst & Ra & cpn=0 & fsbi=1 & OffImm12s { + Fst = *Ra; + Ra = Ra + OffImm12s; +} + +# LDC0 + +:fldi Fdt, AddrRaImm12s is $(I32) & $(LDC) & Fdt & cpn=0 & fsbi=0 & AddrRaImm12s { + Fdt = *AddrRaImm12s; +} + +:fldi.bi Fdt [Ra], OffImm12s is $(I32) & $(LDC) & Fdt & Ra & cpn=0 & fsbi=1 & OffImm12s { + Fdt = *Ra; + Ra = Ra + OffImm12s; +} + +# SWC0 + +:fssi Fst, AddrRaImm12s is $(I32) & $(SWC) & Fst & cpn=0 & fsbi=0 & AddrRaImm12s { + *AddrRaImm12s = Fst; +} + +:fssi.bi Fst [Ra], OffImm12s is $(I32) & $(SWC) & Fst & Ra & cpn=0 & fsbi=1 & OffImm12s { + *Ra = Fst; + Ra = Ra + OffImm12s; +} + +# SDC0 +:fsdi Fdt, AddrRaImm12s is $(I32) & $(SDC) & Fdt & cpn=0 & fsbi=0 & AddrRaImm12s { + *AddrRaImm12s = Fdt; +} + +:fsdi.bi Fdt [Ra], OffImm12s is $(I32) & $(SDC) & Fdt & Ra & cpn=0 & fsbi=1 & OffImm12s { + *Ra = Fdt; + Ra = Ra + OffImm12s; +} + +:fmfcfg Rt is $(I32) & $(COP) & fop4=0xc & Rt & f2op=0x0 & cop4=0x1 { + Rt = fpcfg; +} + +:fmfcsr Rt is $(I32) & $(COP) & fop4=0xc & Rt & f2op=0x1 & cop4=0x1 { + Rt = fpcsr; +} + +:fmtcsr Rt is $(I32) & $(COP) & fop4=0xc & Rt & Fsa & f2op=0x1 & cop4=0x9 { + fpcsr = Rt; +} + diff --git a/pypcode/processors/NDS32/data/languages/nds32be.slaspec b/pypcode/processors/NDS32/data/languages/nds32be.slaspec new file mode 100644 index 00000000..24436422 --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32be.slaspec @@ -0,0 +1,3 @@ +@define ENDIAN "big" + +@include "nds32.sinc" diff --git a/pypcode/processors/NDS32/data/languages/nds32le.slaspec b/pypcode/processors/NDS32/data/languages/nds32le.slaspec new file mode 100644 index 00000000..d6d998cd --- /dev/null +++ b/pypcode/processors/NDS32/data/languages/nds32le.slaspec @@ -0,0 +1,3 @@ +@define ENDIAN "little" + +@include "nds32.sinc" diff --git a/pypcode/processors/NDS32/data/patterns/nds32_patterns.xml b/pypcode/processors/NDS32/data/patterns/nds32_patterns.xml new file mode 100644 index 00000000..802d6307 --- /dev/null +++ b/pypcode/processors/NDS32/data/patterns/nds32_patterns.xml @@ -0,0 +1,12 @@ + + + + 0xfc 1....... + 0xdd 0x9e + + + 0xfc 0....... + + + + \ No newline at end of file diff --git a/pypcode/processors/NDS32/data/patterns/patternconstraints.xml b/pypcode/processors/NDS32/data/patterns/patternconstraints.xml new file mode 100644 index 00000000..735a59be --- /dev/null +++ b/pypcode/processors/NDS32/data/patterns/patternconstraints.xml @@ -0,0 +1,5 @@ + + + nds32_patterns.xml + + diff --git a/pypcode/processors/PA-RISC/data/languages/pa-risc.opinion b/pypcode/processors/PA-RISC/data/languages/pa-risc.opinion index 240b4895..92bd17ca 100644 --- a/pypcode/processors/PA-RISC/data/languages/pa-risc.opinion +++ b/pypcode/processors/PA-RISC/data/languages/pa-risc.opinion @@ -1,5 +1,10 @@ - + + + + + + diff --git a/pypcode/processors/PIC/data/languages/PIC24.sinc b/pypcode/processors/PIC/data/languages/PIC24.sinc index 1242db58..c31fcbf8 100644 --- a/pypcode/processors/PIC/data/languages/PIC24.sinc +++ b/pypcode/processors/PIC/data/languages/PIC24.sinc @@ -3456,8 +3456,8 @@ define pcodeop contextswap; local div:2 = sext(TOK_10_7_Wreg) s/ sext(TOK_3_0_Wreg); local rem:2 = sext(TOK_10_7_Wreg) s% sext(TOK_3_0_Wreg); - W0 = div:1; - W1 = rem:1; + W0 = zext(div:1); + W1 = zext(rem:1); testSRL_N ( W1 ); @@ -3545,8 +3545,8 @@ define pcodeop isDivideOverflow; local div:2 = zext(TOK_10_7_Wreg) / zext(TOK_3_0_Wreg); local rem:2 = zext(TOK_10_7_Wreg) % zext(TOK_3_0_Wreg); - W0 = div:1; - W1 = rem:1; + W0 = zext(div:1); + W1 = zext(rem:1); testSRL_N ( W1 ); @@ -7204,13 +7204,13 @@ define pcodeop pwrsavOp; :sac.d ACCA_t^r4_t,Wsnd_t is OP_23_16=0xDC & OP_14=0x0 & OP_7_4=0x0 & ACCA_t & r4_t & Wsnd_t { local tmp:6 = ACCA s>> (16 + r4_t); - Wsnd_t = tmp:2; + Wsnd_t = tmp:4; } :sac.d ACCB_t^r4_t,Wsnd_t is OP_23_16=0xDC & OP_14=0x0 & OP_7_4=0x0 & ACCB_t & r4_t & Wsnd_t { local tmp:6 = ACCB s>> (16 + r4_t); - Wsnd_t = tmp:2; + Wsnd_t = tmp:4; } @endif diff --git a/pypcode/processors/PowerPC/data/languages/SPE_APU.sinc b/pypcode/processors/PowerPC/data/languages/SPE_APU.sinc index 9a3c3686..2c6d481b 100644 --- a/pypcode/processors/PowerPC/data/languages/SPE_APU.sinc +++ b/pypcode/processors/PowerPC/data/languages/SPE_APU.sinc @@ -2038,9 +2038,9 @@ define pcodeop VectorMultiplyWordHighSignedSaturateFractionalToAccumulator2; # RT.h = temp.l; lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32); - lo = lo:4; + lo = zext(lo:4); hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); - hi = hi:4; + hi = zext(hi:4); D = (( zext(hi) << 32) | zext(lo) ); } @@ -2056,9 +2056,9 @@ define pcodeop VectorMultiplyWordHighSignedSaturateFractionalToAccumulator2; # ACC = RT; lo:$(REGISTER_SIZE) = (( A & (0x0000000000000000) ) >> 32) * (( B & (0x0000000000000000) ) >> 32); - lo = lo:4; + lo = zext(lo:4); hi:$(REGISTER_SIZE) = (( A & (0xFFFFFFFF00000000) ) >> 32) * (( B & (0xFFFFFFFF00000000) ) >> 32); - hi = hi:4; + hi = zext(hi:4); D = (( zext(hi) << 32) | zext(lo) ); ACC = D; } diff --git a/pypcode/processors/PowerPC/data/languages/altivec.sinc b/pypcode/processors/PowerPC/data/languages/altivec.sinc index 7f4b339b..720a3df0 100644 --- a/pypcode/processors/PowerPC/data/languages/altivec.sinc +++ b/pypcode/processors/PowerPC/data/languages/altivec.sinc @@ -1764,7 +1764,8 @@ define pcodeop altv300_71; { local offs:2 = (12 - zext(A[0,4])) * 8; local out:16 = (vrB >> offs) & 0xffffffff; - D = out:4; + # No need for zext, as mask is already applied + D = out:$(REGISTER_SIZE); } :vextuwrx D,A,vrB is OP=4 & D & A & vrB & XOP_0_10=1933 { diff --git a/pypcode/processors/PowerPC/data/languages/ppc.ldefs b/pypcode/processors/PowerPC/data/languages/ppc.ldefs index 96b06b6b..22e832ab 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc.ldefs +++ b/pypcode/processors/PowerPC/data/languages/ppc.ldefs @@ -5,13 +5,13 @@ endian="big" size="32" variant="default" - version="1.6" + version="1.7" slafile="ppc_32_be.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:BE:32:default"> PowerPC 32-bit big endian w/Altivec, G2 - + @@ -23,14 +23,14 @@ endian="little" size="32" variant="default" - version="1.6" + version="1.7" slafile="ppc_32_le.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:LE:32:default"> PowerPC 32-bit little endian w/Altivec, G2 - - + + @@ -39,13 +39,13 @@ endian="big" size="64" variant="default" - version="1.6" + version="1.7" slafile="ppc_64_be.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:BE:64:default"> PowerPC 64-bit big endian w/Altivec, G2 - + @@ -57,7 +57,7 @@ endian="big" size="32" variant="64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_be.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerPC.idx" @@ -75,7 +75,7 @@ endian="little" size="32" variant="64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_le.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerPC.idx" @@ -92,13 +92,13 @@ endian="little" size="64" variant="default" - version="1.6" + version="1.7" slafile="ppc_64_le.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:LE:64:default"> PowerPC 64-bit little endian w/Altivec, G2 - + @@ -109,13 +109,13 @@ endian="big" size="32" variant="4xx" - version="1.6" + version="1.7" slafile="ppc_32_4xx_be.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:BE:32:4xx"> PowerPC 4xx 32-bit big endian embedded core - + @@ -126,14 +126,14 @@ endian="little" size="32" variant="4xx" - version="1.6" + version="1.7" slafile="ppc_32_4xx_le.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:LE:32:4xx"> PowerPC 4xx 32-bit little endian embedded core - - + + @@ -142,13 +142,13 @@ endian="big" size="32" variant="MPC8270" - version="1.6" + version="1.7" slafile="ppc_32_quicciii_be.sla" processorspec="ppc_32_mpc8270.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:BE:32:MPC8270"> Freescale MPC8280 32-bit big endian family (PowerQUICC-III) - + @@ -159,13 +159,13 @@ endian="big" size="32" variant="PowerQUICC-III" - version="1.6" + version="1.7" slafile="ppc_32_quicciii_be.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:BE:32:QUICC"> PowerQUICC-III 32-bit big endian family - + @@ -176,14 +176,14 @@ endian="little" size="32" variant="PowerQUICC-III" - version="1.6" + version="1.7" slafile="ppc_32_quicciii_le.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" id="PowerPC:LE:32:QUICC"> PowerQUICC-III 32-bit little endian family - - + + @@ -208,7 +208,7 @@ endian="big" size="32" variant="PowerQUICC-III-e500" - version="1.6" + version="1.7" slafile="ppc_32_e500_be.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" @@ -226,7 +226,7 @@ endian="little" size="32" variant="PowerQUICC-III-e500" - version="1.6" + version="1.7" slafile="ppc_32_e500_le.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" @@ -242,7 +242,7 @@ endian="big" size="32" variant="PowerQUICC-III-e500mc" - version="1.6" + version="1.7" slafile="ppc_32_e500mc_be.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" @@ -259,7 +259,7 @@ endian="little" size="32" variant="PowerQUICC-III-e500mc" - version="1.6" + version="1.7" slafile="ppc_32_e500mc_le.sla" processorspec="ppc_32.pspec" manualindexfile="../manuals/PowerPC.idx" @@ -274,7 +274,7 @@ endian="big" size="32" variant="PowerISA-64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_isa_be.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" @@ -292,7 +292,7 @@ endian="little" size="32" variant="PowerISA-64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_isa_le.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" @@ -309,7 +309,7 @@ endian="big" size="32" variant="PowerISA-Altivec-64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_isa_altivec_be.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" @@ -327,7 +327,7 @@ endian="little" size="32" variant="PowerISA-Altivec-64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_isa_altivec_le.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" @@ -344,13 +344,13 @@ endian="big" size="64" variant="PowerISA-Altivec" - version="1.6" + version="1.7" slafile="ppc_64_isa_altivec_be.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" id="PowerPC:BE:64:A2ALT"> Power ISA 3.0 Big Endian w/Altivec - + @@ -361,13 +361,13 @@ endian="little" size="64" variant="PowerISA-Altivec" - version="1.6" + version="1.7" slafile="ppc_64_isa_altivec_le.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" id="PowerPC:LE:64:A2ALT"> Power ISA 3.0 Little Endian w/Altivec - + @@ -378,7 +378,7 @@ endian="big" size="32" variant="PowerISA-VLE-64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_isa_vle_be.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" @@ -393,7 +393,7 @@ endian="big" size="32" variant="PowerISA-VLE-Altivec-64-32addr" - version="1.6" + version="1.7" slafile="ppc_64_isa_altivec_vle_be.sla" processorspec="ppc_64.pspec" manualindexfile="../manuals/PowerISA.idx" diff --git a/pypcode/processors/PowerPC/data/languages/ppc.ldefs.orig b/pypcode/processors/PowerPC/data/languages/ppc.ldefs.orig new file mode 100644 index 00000000..f38a21c0 --- /dev/null +++ b/pypcode/processors/PowerPC/data/languages/ppc.ldefs.orig @@ -0,0 +1,391 @@ + + + + + PowerPC 32-bit big endian w/Altivec, G2 + + + + + + + + + + PowerPC 32-bit little endian w/Altivec, G2 + + + + + + + + PowerPC 64-bit big endian w/Altivec, G2 + + + + + + + + + + PowerPC 64-bit big endian w/Altivec and 32 bit addressing, G2 + + + + + + + + + + PowerPC 64-bit little endian w/Altivec and 32 bit addressing, G2 + + + + + + + + + PowerPC 64-bit little endian w/Altivec, G2 + + + + + + + + + PowerPC 4xx 32-bit big endian embedded core + + + + + + + + + PowerPC 4xx 32-bit little endian embedded core + + + + + + + + Freescale MPC8280 32-bit big endian family (PowerQUICC-III) + + + + + + + + + PowerQUICC-III 32-bit big endian family + + + + + + + + + PowerQUICC-III 32-bit little endian family + + + + + + + + PowerQUICC-III e500 32-bit big-endian family + + + + + + + + + + PowerQUICC-III e500 32-bit little-endian family + + + + + + + + PowerQUICC-III e500mc 32-bit big-endian family + + + + + + + + + PowerQUICC-III e500mc 32-bit little-endian family + + + + + + + Power ISA 3.0 Big Endian w/EVX and 32-bit Addressing + + + + + + + + + + Power ISA 3.0 Little Endian w/EVX and 32-bit Addressing + + + + + + + + + Power ISA 3.0 Big Endian w/Altivec and 32-bit Addressing + + + + + + + + + + Power ISA 3.0 Little Endian w/Altivec and 32-bit Addressing + + + + + + + + + Power ISA 3.0 Big Endian w/Altivec + + + + + + + + + Power ISA 3.0 Little Endian w/Altivec + + + + + + + + + Power ISA 3.0 Big Endian w/VLE, EVX and 32-bit Addressing + + + + + + + Power ISA 3.0 Big Endian w/VLE, Altivec and 32-bit Addressing + + + + + + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_32_le.cspec b/pypcode/processors/PowerPC/data/languages/ppc_32.cspec similarity index 70% rename from pypcode/processors/PowerPC/data/languages/ppc_32_le.cspec rename to pypcode/processors/PowerPC/data/languages/ppc_32.cspec index 655b4b1a..4b87c035 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_32_le.cspec +++ b/pypcode/processors/PowerPC/data/languages/ppc_32.cspec @@ -32,21 +32,6 @@ - - - - - - - - - - - - - - - @@ -74,6 +59,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -82,9 +87,17 @@ - - + + + + + + + + + + @@ -108,10 +121,33 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_64_be.cspec b/pypcode/processors/PowerPC/data/languages/ppc_64_be.cspec new file mode 100644 index 00000000..eac4523a --- /dev/null +++ b/pypcode/processors/PowerPC/data/languages/ppc_64_be.cspec @@ -0,0 +1,203 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + # Inject pcode when returning from a function call to place the r2Save + # value into 0x28(r1) which should be restored by the "ld r2,0x28(r1)" + # which immediately follows calls which comply with the PPC64 ABI spec. + local saveR2ptr = r1 + 0x28; + *:8 saveR2ptr = r2Save; + + + + + diff --git a/pypcode/processors/PowerPC/data/languages/ppc_64.cspec b/pypcode/processors/PowerPC/data/languages/ppc_64_le.cspec similarity index 58% rename from pypcode/processors/PowerPC/data/languages/ppc_64.cspec rename to pypcode/processors/PowerPC/data/languages/ppc_64_le.cspec index 7220be77..f6f8ecbf 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_64.cspec +++ b/pypcode/processors/PowerPC/data/languages/ppc_64_le.cspec @@ -1,8 +1,28 @@ + - + + + + + + + + + + + + + + + + + + + @@ -50,33 +70,49 @@ - + - + - + - + - + - + - + - + + + + + + + + + + + + + + + + + @@ -85,6 +121,14 @@ + + + + + + + + @@ -109,7 +153,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + # Inject pcode when returning from a function call to place the r2Save diff --git a/pypcode/processors/PowerPC/data/languages/ppc_common.sinc b/pypcode/processors/PowerPC/data/languages/ppc_common.sinc index 3a3d9a2e..828f4c26 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_common.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_common.sinc @@ -1862,8 +1862,8 @@ TOm: "" is TO { } CTR_DEC: "z" is BO_3=1 {CTR = CTR-1; tmp:1 = (CTR == 0); export tmp; } CTR_DEC: "nz" is BO_3=0 {CTR = CTR-1; tmp:1 = (CTR != 0); export tmp; } -CC_TF: "t" is BO_1=1 {} -CC_TF: "f" is BO_1=0 {} +CC_TF: "t" is BO_1=1 { tmp:1 = 1; export tmp; } +CC_TF: "f" is BO_1=0 { tmp:1 = 0; export tmp; } # OP=19 & CC_D_OP & CC_OP & CC_B_OP & CR_D & CR_D_CC & XOP_1_10=129 & BIT_0=0 diff --git a/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc b/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc index bc731d6b..fd17f4fd 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_instructions.sinc @@ -438,7 +438,7 @@ #bdnzf 4*cr2+eq,LAB_0000 0x40 0a 00 00 :bd^CTR_DEC^CC_TF^REL_ABS CC_OP,addressBD is $(NOTVLE) & OP=16 & CC_TF & REL_ABS & CTR_DEC & CC_OP & addressBD & BO_0=0 & BO_2=0 & LK=0 { - if (CTR_DEC && CC_OP) goto addressBD; + if (CTR_DEC && (CC_OP == CC_TF)) goto addressBD; } #bdzfl lt,FUN_0000 0x40 00 00 01 @@ -447,7 +447,7 @@ [ linkreg=0; globalset(inst_start,linkreg); ] { LR = inst_next; - if (!(CTR_DEC && CC_OP)) goto inst_next; + if (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next; call addressBD; } @@ -688,7 +688,7 @@ :bd^CTR_DEC^CC_TF^"lr" CC_OP is $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BO_0=0 & BO_2=0 & BH=0 & LK=0 & BITS_13_15=0 & XOP_1_10=16 [ linkreg=0; globalset(inst_start,linkreg); ] { - if (!(CTR_DEC && CC_OP)) goto inst_next; + if (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next; goto [LR]; } @@ -697,7 +697,7 @@ :bd^CTR_DEC^CC_TF^"lr" CC_OP,BH is $(NOTVLE) & OP=19 & CC_TF & CTR_DEC & CC_OP & BO_0=0 & BO_2=0 & BH & LK=0 & BITS_13_15=0 & XOP_1_10=16 [ linkreg=0; globalset(inst_start,linkreg); ] { - if (!(CTR_DEC && CC_OP)) goto inst_next; + if (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next; goto [LR]; } @@ -708,7 +708,7 @@ { tmp:$(REGISTER_SIZE) = LR; LR = inst_next; - if (!(CTR_DEC && CC_OP)) goto inst_next; + if (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next; call [tmp]; } @@ -719,7 +719,7 @@ { tmp:$(REGISTER_SIZE) = LR; LR = inst_next; - if (!(CTR_DEC && CC_OP)) goto inst_next; + if (!(CTR_DEC && (CC_OP == CC_TF))) goto inst_next; call [tmp]; } diff --git a/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc b/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc index 510bf963..7b08e4b5 100644 --- a/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc +++ b/pypcode/processors/PowerPC/data/languages/ppc_vle.sinc @@ -34,14 +34,11 @@ sd4WPlusRxAddr: SD4_OFF(RX_VLE) is SD4_VLE & RX_VLE [SD4_OFF = SD4_VLE << 2;] { OIMM: val is UI5_VLE [ val = UI5_VLE+1; ] { export *[const]:$(REGISTER_SIZE) val; } @if REGISTER_SIZE == "4" -SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFF << ((SCL_VLE*8) + 8)) | (0xFFFFFFFF >> (32 - (SCL_VLE*8)))) * BIT_10) | (IMM8 << (SCL_VLE*8)); ] { export *[const]:4 val;} +SCALE: val is BIT_10=1 & SCL_VLE & IMM8 [ val = (0xFFFFFFFF) & ~((0xFF-IMM8) << (SCL_VLE*8)); ] { export *[const]:4 val;} +SCALE: val is BIT_10=0 & SCL_VLE & IMM8 [ val = (IMM8 << (SCL_VLE*8)); ] { export *[const]:4 val;} @else -# Due to the way this big >> would work in java (arithmetic), we have to modify the orig way this was done. -# (0xFFFFFFFFFFFFFFFF >> (64 - (SCL_VLE*8)) <--- Original -# (0x7FFFFFFFFFFFFFFF >> (63 - (SCL_VLE*8)) <--- New -# We 'pre-shift' by 1 and take 1 off the total we'd shift by. SCL_VLE*8 is at most 24 so we don't have to -# worry about a negative shift value. -SCALE: val is BIT_10 & SCL_VLE & IMM8 [ val = (((0xFFFFFFFFFFFFFFFF << ((SCL_VLE*8) + 8)) | (0x7FFFFFFFFFFFFFFF >> (63 - (SCL_VLE*8)))) * BIT_10) | (IMM8 << (SCL_VLE*8)); ] { export *[const]:8 val;} +SCALE: val is BIT_10=1 & SCL_VLE & IMM8 [ val = (0xFFFFFFFFFFFFFFFF) & ~((0xFF-IMM8) << (SCL_VLE*8)); ] { export *[const]:8 val;} +SCALE: val is BIT_10=0 & SCL_VLE & IMM8 [ val = IMM8 << (SCL_VLE*8); ] { export *[const]:8 val;} @endif SIMM16: val is IMM_0_10_VLE & SIMM_21_25_VLE [ val = (SIMM_21_25_VLE << 11) | IMM_0_10_VLE ;] { export *[const]:2 val; } @@ -695,10 +692,15 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | D = D | tmp; } +:e_nop is $(ISVLE) & OP=6 & XOP_12_VLE=13 & BITS_1_10=0 & BIT_0=0 & S=0 & A=0 { + +} + :e_ori A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=13 & BIT_11=0 & S & A & SCALE { A = S | SCALE; } + :e_ori. A,S,SCALE is $(ISVLE) & OP=6 & XOP_12_VLE=13 & BIT_11=1 & S & A & SCALE { A = S | SCALE; cr0flags(A); @@ -726,6 +728,10 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) | RX_VLE = RX_VLE & ~RY_VLE; } +:se_nop is $(ISVLE) & OP6_VLE=17 & BITS_8_9=0 & RX_VLE=0 & RY_VLE=0 { + +} + :se_or RX_VLE,RY_VLE is $(ISVLE) & OP6_VLE=17 & BITS_8_9=0 & RX_VLE & RY_VLE { RX_VLE = RX_VLE | RY_VLE; } diff --git a/pypcode/processors/PowerPC/data/patterns/PPC_BE_patterns.xml b/pypcode/processors/PowerPC/data/patterns/PPC_BE_patterns.xml index d69520f0..2937da4e 100644 --- a/pypcode/processors/PowerPC/data/patterns/PPC_BE_patterns.xml +++ b/pypcode/processors/PowerPC/data/patterns/PPC_BE_patterns.xml @@ -73,4 +73,18 @@ + + + 011111.. ...01000 0x02 0xa6 + 0x42 1....... 0x00 0x05 + 011111.. ...01000 0x02 0xa6 + 001111.. ........ 0x.. 0x.. + 001110.. ........ 0x.. 0x.. + 011111.. ...01000 0x03 0xa6 + 011111.. ...01001 0x03 0xa6 + 0x4e 10000... 0x04 0x20 + + + + diff --git a/pypcode/processors/PowerPC/data/patterns/PPC_BE_prepatterns.xml b/pypcode/processors/PowerPC/data/patterns/PPC_BE_prepatterns.xml new file mode 100644 index 00000000..a3e7ef70 --- /dev/null +++ b/pypcode/processors/PowerPC/data/patterns/PPC_BE_prepatterns.xml @@ -0,0 +1,208 @@ + + + + + 0xf8410028 + 001111.. ...00010 0xff 0xff + 0xe9 ........ ........ ........ + 0x7d 0x.9 0x03 0xa6 + 0xe8 010..... ........ ........ + 0x28220000 + 0x4c 1..00010 0x04 0x20 + 010010.. ........ ........ ......00 + + + + + + + 0xf8410028 + 0xe9 ........ ........ ........ + 0x7d 0x.9 0x03 0xa6 + 0xe8 010..... ........ ........ + 0x28220000 + 0x4c 1..00010 0x04 0x20 + 010010.. ........ ........ ......00 + + + + + + + 011111.. ...01000 0x02 0xa6 + 0x42 1....... 0x00 0x05 + 011111.. ...01000 0x02 0xa6 + 001111.. ........ 0x.. 0x.. + 001110.. ........ 0x.. 0x.. + 011111.. ...01000 0x03 0xa6 + 011111.. ...01001 0x03 0xa6 + 0x4e 10000... 0x04 0x20 + + + + + + + + 0x....823d # addis r12,r2,0x#### + 0x..0041f8 # std r2,0x##(r1) + 0x....6ce9 # ld r11,0x####(r12) + 0xa603697d # mtspr CTR,r11 + 0x....4ce8 # ld r2,0x####(r12) + 0x....6ce9 # ld r11,0x####(r12) + 0x2004804e # bctr + + + + + + 0x..0041f8 # std r2,0x##(r1) + 0x....62e9 # ld r11,0x####(r2) + 0xa603697d # mtspr CTR,r11 + 0x....62e9 # ld r11,0x####(r2) + 0x....42e8 # ld r2,0x####(r2) + 0x2004804e # bctr + + + + + + 0x..0041f8 # std r2,0x##(r1) + 0x....82e9 # ld r12,0x####(r2) + 0xa603897d # mtspr CTR,r12 + 0x2004804e # bctr + + + + + + + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0xa603897d # mtspr CTR,r12 + 0x....4be8 # ld r2,0x####(r11) + 0x2004804e # bctr + + + + + + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0x....6b39 # addi r11,r11,0x#### + 0xa603897d # mtspr CTR,r12 + 0x....4be8 # ld r2,0x####(r11) + 0x....6be9 # ld r11,0x####(r11) + 0x2004804e # bctr + + + + + + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0xa603897d # mtspr CTR,r12 + 0x7862827d # xor r2,r12,r12 + 0x14126b7d # add r11,r11,r2 + 0x....4be8 # ld r2,0x####(r11) + 0x2004804e # bctr + + + + + + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0x....6b39 # addi r11,r11,0x#### + 0xa603897d # mtspr CTR,r12 + 0x7862827d # xor r2,r12,r12 + 0x14126b7d # add r11,r11,r2 + 0x....4be8 # ld r2,0x####(r11) + 0x....6be9 # ld r11,0x####(r11) + 0x2004804e # bctr + + + + + + 0x..0041f8 # std r2,0x##(r1) + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0xa603897d # mtspr CTR,r12 + 0x....4be8 # ld r2,0x####(r11) + 0x2004804e # bctr + + + + + + 0x..0041f8 # std r2,0x##(r1) + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0x....6b39 # addi r11,r11,0x#### + 0xa603897d # mtspr CTR,r12 + 0x....4be8 # ld r2,0x####(r11) + 0x....6be9 # ld r11,0x####(r11) + 0x2004804e # bctr + + + + + + 0x..0041f8 # std r2,0x##(r1) + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0xa603897d # mtspr CTR,r12 + 0x7862827d # xor r2,r12,r12 + 0x14126b7d # add r11,r11,r2 + 0x....4be8 # ld r2,0x####(r11) + 0x2004804e # bctr + + + + + + 0x..0041f8 # std r2,0x##(r1) + 0x....623d # addis r11,r2,0x#### + 0x....8be9 # ld r12,0x####(r11) + 0x....6b39 # addi r11,r11,0x#### + 0xa603897d # mtspr CTR,r12 + 0x7862827d # xor r2,r12,r12 + 0x14126b7d # add r11,r11,r2 + 0x....4be8 # ld r2,0x####(r11) + 0x....6be9 # ld r11,0x####(r11) + 0x2004804e # bctr + + + + + + + 0x0000823d # addis r12,r2,0x#### + 0x00008ce9 # ld r12,0x####(r12) + 0xa603897d # mtspr CTR,r12 + 0x2004804e # bctr + + + + + + 0x000041f8 # std r2,0x####(r1) + 0x0000823d # addis r12,r2,0x#### + 0x00008ce9 # ld r12,0x####(r12) + 0xa603897d # mtspr CTR,r12 + 0x2004804e # bctr + + + + diff --git a/pypcode/processors/PowerPC/data/patterns/PPC_LE_patterns.xml b/pypcode/processors/PowerPC/data/patterns/PPC_LE_patterns.xml index 6e4e7b73..8d22aafc 100644 --- a/pypcode/processors/PowerPC/data/patterns/PPC_LE_patterns.xml +++ b/pypcode/processors/PowerPC/data/patterns/PPC_LE_patterns.xml @@ -73,4 +73,18 @@ + + + 0xa6 0x02 ...01000 011111.. + 0x05 0x00 1....... 0x42 + 0xa6 0x02 ...01000 011111.. + 0x.. 0x.. ........ 001111.. + 0x.. 0x.. ........ 001110.. + 0xa6 0x03 ...01000 011111.. + 0xa6 0x03 ...01001 011111.. + 0x20 0x04 10000... 0x4e + + + + diff --git a/pypcode/processors/PowerPC/data/ppc64-r2CallStubs.xml b/pypcode/processors/PowerPC/data/patterns/PPC_LE_prepatterns.xml similarity index 60% rename from pypcode/processors/PowerPC/data/ppc64-r2CallStubs.xml rename to pypcode/processors/PowerPC/data/patterns/PPC_LE_prepatterns.xml index 5be83ca9..e467dc3a 100644 --- a/pypcode/processors/PowerPC/data/ppc64-r2CallStubs.xml +++ b/pypcode/processors/PowerPC/data/patterns/PPC_LE_prepatterns.xml @@ -1,12 +1,52 @@ - + + + + + 0x280041f8 + 0xff 0xff ...00010 001111.. + ........ ........ ........ 0xe9 + 0xa6 0x03 0x.9 0x7d + ........ ........ 010..... 0xe8 + 0x00002228 + 0x20 0x04 1..00010 0x4c + ......00 ........ ........ 010010.. + + + + + + + 0x280041f8 + ........ ........ ........ 0xe9 + 0xa6 0x03 0x.9 0x7d + ........ ........ 010..... 0xe8 + 0x00002228 + 0x20 0x04 1..00010 0x4c + ......00 ........ ........ 010010.. + + + + + + + 0xa6 0x02 ...01000 011111.. + 0x05 0x00 1....... 0x42 + 0xa6 0x02 ...01000 011111.. + 0x.. 0x.. ........ 001111.. + 0x.. 0x.. ........ 001110.. + 0xa6 0x03 ...01000 011111.. + 0xa6 0x03 ...01001 011111.. + 0x20 0x04 10000... 0x4e + + + + @@ -18,6 +58,7 @@ 0xe96c.... # ld r11,0x####(r12) 0x4e800420 # bctr + @@ -28,6 +69,7 @@ 0xe842.... # ld r2,0x####(r2) 0x4e800420 # bctr + @@ -36,6 +78,7 @@ 0x7d8903a6 # mtspr CTR,r12 0x4e800420 # bctr + @@ -46,6 +89,7 @@ 0xe84b.... # ld r2,0x####(r11) 0x4e800420 # bctr + @@ -57,6 +101,7 @@ 0xe96b.... # ld r11,0x####(r11) 0x4e800420 # bctr + @@ -68,6 +113,7 @@ 0xe84b.... # ld r2,0x####(r11) 0x4e800420 # bctr + @@ -81,6 +127,7 @@ 0xe96b.... # ld r11,0x####(r11) 0x4e800420 # bctr + @@ -91,6 +138,7 @@ 0xe84b.... # ld r2,0x####(r11) 0x4e800420 # bctr + @@ -103,6 +151,7 @@ 0xe96b.... # ld r11,0x####(r11) 0x4e800420 # bctr + @@ -115,6 +164,7 @@ 0xe84b.... # ld r2,0x####(r11) 0x4e800420 # bctr + @@ -129,6 +179,7 @@ 0xe96b.... # ld r11,0x####(r11) 0x4e800420 # bctr + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/RISCV/data/languages/RV32G.pspec b/pypcode/processors/RISCV/data/languages/RV32G.pspec deleted file mode 100644 index b3b2a714..00000000 --- a/pypcode/processors/RISCV/data/languages/RV32G.pspec +++ /dev/null @@ -1,19 +0,0 @@ - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV32GC.pspec b/pypcode/processors/RISCV/data/languages/RV32GC.pspec deleted file mode 100644 index 133923e1..00000000 --- a/pypcode/processors/RISCV/data/languages/RV32GC.pspec +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV32I.pspec b/pypcode/processors/RISCV/data/languages/RV32I.pspec deleted file mode 100644 index 7ece09e0..00000000 --- a/pypcode/processors/RISCV/data/languages/RV32I.pspec +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV32IC.pspec b/pypcode/processors/RISCV/data/languages/RV32IC.pspec deleted file mode 100644 index 148daf44..00000000 --- a/pypcode/processors/RISCV/data/languages/RV32IC.pspec +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV32IMC.pspec b/pypcode/processors/RISCV/data/languages/RV32IMC.pspec deleted file mode 100644 index b9f539d2..00000000 --- a/pypcode/processors/RISCV/data/languages/RV32IMC.pspec +++ /dev/null @@ -1,16 +0,0 @@ - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV64.pspec b/pypcode/processors/RISCV/data/languages/RV64.pspec new file mode 100644 index 00000000..91a024a8 --- /dev/null +++ b/pypcode/processors/RISCV/data/languages/RV64.pspec @@ -0,0 +1,425 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/RISCV/data/languages/RV64G.pspec b/pypcode/processors/RISCV/data/languages/RV64G.pspec deleted file mode 100644 index dcf939f3..00000000 --- a/pypcode/processors/RISCV/data/languages/RV64G.pspec +++ /dev/null @@ -1,19 +0,0 @@ - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV64GC.pspec b/pypcode/processors/RISCV/data/languages/RV64GC.pspec deleted file mode 100644 index 2e75cb4f..00000000 --- a/pypcode/processors/RISCV/data/languages/RV64GC.pspec +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV64I.pspec b/pypcode/processors/RISCV/data/languages/RV64I.pspec deleted file mode 100644 index 726e53df..00000000 --- a/pypcode/processors/RISCV/data/languages/RV64I.pspec +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/RV64IC.pspec b/pypcode/processors/RISCV/data/languages/RV64IC.pspec deleted file mode 100644 index 0944cda1..00000000 --- a/pypcode/processors/RISCV/data/languages/RV64IC.pspec +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/pypcode/processors/RISCV/data/languages/andestar_v5.instr.sinc b/pypcode/processors/RISCV/data/languages/andestar_v5.instr.sinc new file mode 100644 index 00000000..c6298812 --- /dev/null +++ b/pypcode/processors/RISCV/data/languages/andestar_v5.instr.sinc @@ -0,0 +1,608 @@ +# +# AndeStar V5 extensions to base RISC-V architecture +# + +# +# ExecTable is loaded/overlayed on the memory segment +# That is indexed by the E +define space ExecTable type=ram_space size=2; + +@define CUSTOM0 "op0006=0b0001011" +@define CUSTOM1 "op0006=0b0101011" +@define CUSTOM2 "op0006=0b1011011" +@define CUSTOM4 "op0006=0b1010111" + +simm18_lb: val is sop3131 & op1516 & op1719 & op2020 & op2130 & op1414 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2130<<1) | op1414; ] { + export *[const]:$(XLEN) val; +} + +simm18_lh: val is sop3131 & op1516 & op1719 & op2020 & op2130 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2130<<1); ] { + export *[const]:$(XLEN) val; +} + +#simm18_lw: val is sop3131 & op1516 & op1719 & op2020 & op2130 [ val = (sop3131<<18) | (op1516<<16) | (op1719<<13) | (op2020<<12) | (op2130<<2); ] { +simm18_lw: val is sop3131 & op2121 & op1516 & op1719 & op2020 & op2230 [ val = (sop3131<<18) | (op2121 << 17) | (op1516<<15) | (op1719<<12) | (op2020<<11) | (op2230<<2); ] { + export *[const]:$(XLEN) val; +} + +simm18_ld: val is sop3131 & op1516 & op1719 & op2020 & op2122 & op2330 [ val = (sop3131<<19) | (op2122<<17) | (op1516<<15) | (op1719<<12) | (op2330<<3); ] { + export *[const]:$(XLEN) val; +} + +simm18_sb: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0811 & op1414 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0811<<1) | op1414; ] { + export *[const]:$(XLEN) val; +} + +simm18_sh: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0811 [ val = (sop3131<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0811<<1); ] { + export *[const]:$(XLEN) val; +} + +simm18_sw: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0808 & op0911 [ val = (sop3131<<18) | (op0808<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op0911<<2); ] { + export *[const]:$(XLEN) val; +} + +simm18_sd: val is sop3131 & op1516 & op1719 & op0707 & op2530 & op0809 & op1011 [ val = (sop3131<<19) | (op0809<<17) | (op1516<<15) | (op1719<<12) | (op0707<<11) | (op2530<<5) | (op1011<<3); ] { + export *[const]:$(XLEN) val; +} + +cimm: "#"^val is op2024 & op0707 [ val = op0707<<5 | op2024; ] { + # Note on 32-bit op0707 must be 0 + export *[const]:$(XLEN) val; +} + +cimm7: "#"^val is op3030 & op2024 & op0707 [ val = op3030<<6 | op0707<<5 | op2024; ] { + export *[const]:$(XLEN) val; +} + +ra_imm10: dest is sop3131 & op2529 & op0811 [ dest = inst_start + (sop3131 << 10 | op2529<<5 | op0811<<1); ] { + export *[ram]:$(XLEN) dest; +} + + +:addigp rd,simm18_lb is simm18_lb & rd & op1213=1 & $(CUSTOM0) +{ + rd = gp + simm18_lb; +} + +:bbc rs1,cimm,ra_imm10 is rs1 & cimm & ra_imm10 & op3030=0 & op1214=0b111 & op0707=0 & $(CUSTOM2) +{ + tst:1 = (rs1 & (1 << cimm)) == 0; + if (tst) goto ra_imm10; +} + +:bbs rs1,cimm,ra_imm10 is rs1 & cimm & ra_imm10 & op3030=1 & op1214=0b111 & op0707=0 & $(CUSTOM2) +{ + tst:1 = (rs1 & (1 << cimm)) == 1; + if (tst) goto ra_imm10; +} + +:beqc rs1,cimm7,ra_imm10 is rs1 & cimm7 & ra_imm10 & op1214=0b101 & $(CUSTOM2) +{ + tst:1 = rs1 == cimm7; + if (tst) goto ra_imm10; +} + +:bnec rs1,cimm7,ra_imm10 is rs1 & cimm7 & ra_imm10 & op1214=0b110 & $(CUSTOM2) +{ + tst:1 = rs1 != cimm7; + if (tst) goto ra_imm10; +} + +msb: "#"^op2631 is op2631 { export *[const]:$(XLEN) op2631; } +lsb: "#"^op2025 is op2025 { export *[const]:$(XLEN) op2025; } + +:bfos rd,rs1,msb,lsb is rd & rs1 & op2631=0 & msb & lsb & op1214=0b011 & $(CUSTOM2) +{ + # msb==0 Rd[LSB] = sext(Rs1[0]) + shift:$(XLEN) = ($(XLEN)*8-1); + val:$(XLEN) = (rs1 & 1 << shift) s>> (shift); + val = val << lsb; + rd = val; +} + +:bfos rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 > op2631) & (op2631 != 0) & op1214=0b011 & $(CUSTOM2) +{ + # msb < lsb Rd[LSB:MSB] = sext(Rs1[len-1:0]) + len:$(XLEN) = lsb-msb+1; + shift:$(XLEN) = ($(XLEN)*8 - len); + val:$(XLEN) = (rs1 << shift) s>> shift; + val = val << msb; + rd = val; +} + +:bfos rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 <= op2631) & (op2631 != 0) & op1214=0b011 & $(CUSTOM2) +{ + # msb >= lsb Rd[len-1:0] = sext(Rs1[MSB:LSB]) + len:$(XLEN) = msb-lsb+1; + shift:$(XLEN) = ($(XLEN)*8 - msb - 1); + val:$(XLEN) = (rs1 << shift) s>> ($(XLEN)*8 - len); + rd = val; +} + +:bfoz rd,rs1,msb,lsb is rd & rs1 & op2631=0 & msb & lsb & op1214=0b010 & $(CUSTOM2) +{ + # msb==0 Rd[LSB] = zext(Rs1[0]) + val:$(XLEN) = rs1 & 1; + val = val << lsb; + rd = val; +} + +:bfoz rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 > op2631) & (op2631 != 0) & op1214=0b010 & $(CUSTOM2) +{ + # msb < lsb Rd[LSB:MSB] = zext(Rs1[len-1:0]) + len:$(XLEN) = lsb-msb+1; + mask:$(XLEN) = ((-1) >> ($(XLEN)*8 -len)); + val:$(XLEN) = rs1 & mask; + val = val << msb; + rd = val; +} + +:bfoz rd,rs1,msb,lsb is rd & rs1 & msb & lsb & (op2025 <= op2631) & op1214=0b010 & $(CUSTOM2) +{ + # msb >= lsb Rd[len-1:0] = zext(Rs1[MSB:LSB]) + len:$(XLEN) = msb-lsb+1; + mask:$(XLEN) = ((-1) >> ($(XLEN)*8 -len)) << lsb; + val:$(XLEN) = rs1 & mask; + val = val >> lsb; + rd = val; +} + + + +:lea.h rd,rs1,rs2 is op2531=0b0000101 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2) +{ + local ea:$(XLEN) = rs1 + rs2 * 2; + rd = ea; +} + +:lea.w rd,rs1,rs2 is op2531=0b0000110 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2) +{ + local ea:$(XLEN) = rs1 + rs2 * 4; + rd = ea; +} + +:lea.d rd,rs1,rs2 is op2531=0b0000111 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2) +{ + local ea:$(XLEN) = rs1 + rs2 * 8; + rd = ea; +} + +:lea.b.ze rd,rs1,rs2 is op2531=0b0001000 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2) +{ + local ea:$(XLEN) = rs1 + zext(rs2:4); + rd = ea; +} + +:lea.h.ze rd,rs1,rs2 is op2531=0b0001001 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2) +{ + local ea:$(XLEN) = rs1 + zext(rs2:4) * 2; + rd = ea; +} + +:lea.w.ze rd,rs1,rs2 is op2531=0b0001010 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2) +{ + local ea:$(XLEN) = rs1 + zext(rs2:4) * 4; + rd = ea; +} + +:lea.d.ze rd,rs1,rs2 is op2531=0b0001011 & rs2 & rs1 & op1214=0 & rd & $(CUSTOM2) +{ + local ea:$(XLEN) = rs1 + zext(rs2:4) * 8; + rd = ea; +} + +:lbgp rd,"["^simm18_lb^"]" is simm18_lb & rd & op1213=0 & $(CUSTOM0) +{ + local ea:$(XLEN) = gp + simm18_lb; + rd = sext(*[ram]:1 ea); +} + +:lbugp rd,"["^simm18_lb^"]" is simm18_lb & rd & op1213=2 & $(CUSTOM0) +{ + local ea:$(XLEN) = gp + simm18_lb; + rd = zext(*[ram]:1 ea); +} + +:lhgp rd,"["^simm18_lh^"]" is simm18_lh & rd & op1214=1 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_lh; + rd = sext(*[ram]:2 ea); +} + +:lhugp rd,"["^simm18_lh^"]" is simm18_lh & rd & op1214=5 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_lh; + rd = zext(*[ram]:2 ea); +} + +:lwgp rd,"["^simm18_lw^"]" is simm18_lw & rd & op1214=2 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_lw; + rd = sext(*[ram]:4 ea); +} + +:lwugp rd,"["^simm18_lw^"]" is simm18_lw & rd & op1214=6 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_lw; + rd = zext(*[ram]:4 ea); +} + +:ldgp rd,"["^simm18_ld^"]" is simm18_ld & rd & op1214=3 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_ld; + rd = *[ram]:8 ea; +} + +:sbgp rs2,"["^simm18_sb^"]" is simm18_sb & rs2 & op1213=3 & $(CUSTOM0) +{ + local ea:$(XLEN) = gp + simm18_sb; + *[ram]:1 ea = rs2[0,8]; +} + +:shgp rs2,"["^simm18_sh^"]" is simm18_sh & rs2 & op1214=0 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_sh; + *[ram]:2 ea = rs2[0,16]; +} + +:swgp rs2,"["^simm18_sw^"]" is simm18_sw & rs2 & op1214=4 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_sw; + *[ram]:4 ea = rs2[0,32]; +} + +:sdgp rs2,"["^simm18_sd^"]" is simm18_sd & rs2 & op1214=7 & $(CUSTOM1) +{ + local ea:$(XLEN) = gp + simm18_sd; + *[ram]:8 ea = rs2; +} + + +:ffb rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010000 & op1214=0 & $(CUSTOM2) { +@if XLEN == "4" + m1:1 = (rs1[0,8] == rs2[0,8]); + m2:1 = (rs1[8,8] == rs2[0,8]); + m3:1 = (rs1[16,8] == rs2[0,8]); + m4:1 = (rs1[24,8] == rs2[0,8]); + rd = -4; + if (m1) goto inst_next; + rd = -3; + if (m2) goto inst_next; + rd = -2; + if (m3) goto inst_next; + rd = -1; + if (m4) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1); +@else + m1:1 = (rs1[0,8] == rs2[0,8]); + m2:1 = (rs1[8,8] == rs2[0,8]); + m3:1 = (rs1[16,8] == rs2[0,8]); + m4:1 = (rs1[24,8] == rs2[0,8]); + m5:1 = (rs1[32,8] == rs2[0,8]); + m6:1 = (rs1[40,8] == rs2[0,8]); + m7:1 = (rs1[48,8] == rs2[0,8]); + m8:1 = (rs1[56,8] == rs2[0,8]); + rd = -8; + if (m1) goto inst_next; + rd = -7; + if (m2) goto inst_next; + rd = -6; + if (m3) goto inst_next; + rd = -5; + if (m4) goto inst_next; + rd = -4; + if (m5) goto inst_next; + rd = -3; + if (m6) goto inst_next; + rd = -2; + if (m7) goto inst_next; + rd = -1; + if (m8) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1); +@endif +} + +:ffzmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010001 & op1214=0 & $(CUSTOM2) { +@if XLEN == "4" + m1:1 = (rs1[0,8]==0) | (rs1[0,8] == rs2[0,8]); + m2:1 = (rs1[8,8]==0) | (rs1[8,8] == rs2[8,8]); + m3:1 = (rs1[16,8]==0) | (rs1[16,8] == rs2[16,8]); + m4:1 = (rs1[24,8]==0) | (rs1[24,8] == rs2[24,8]); + rd = -4; + if (m1) goto inst_next; + rd = -3; + if (m2) goto inst_next; + rd = -2; + if (m3) goto inst_next; + rd = -1; + if (m4) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1); +@else + m1:1 = (rs1[0,8]==0) | (rs1[0,8] == rs2[0,8]); + m2:1 = (rs1[8,8]==0) | (rs1[8,8] == rs2[8,8]); + m3:1 = (rs1[16,8]==0) | (rs1[16,8] == rs2[16,8]); + m4:1 = (rs1[24,8]==0) | (rs1[24,8] == rs2[24,8]); + m5:1 = (rs1[32,8]==0) | (rs1[32,8] == rs2[32,8]); + m6:1 = (rs1[40,8]==0) | (rs1[40,8] == rs2[40,8]); + m7:1 = (rs1[48,8]==0) | (rs1[48,8] == rs2[48,8]); + m8:1 = (rs1[56,8]==0) | (rs1[56,8] == rs2[56,8]); + rd = -8; + if (m1) goto inst_next; + rd = -7; + if (m2) goto inst_next; + rd = -6; + if (m3) goto inst_next; + rd = -5; + if (m4) goto inst_next; + rd = -4; + if (m5) goto inst_next; + rd = -3; + if (m6) goto inst_next; + rd = -2; + if (m7) goto inst_next; + rd = -1; + if (m8) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1); +@endif +} + +:ffmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010010 & op1214=0 & $(CUSTOM2) { +@if XLEN == "4" + m1:1 = (rs1[0,8] != rs2[0,8]); + m2:1 = (rs1[8,8] != rs2[8,8]); + m3:1 = (rs1[16,8] != rs2[16,8]); + m4:1 = (rs1[24,8] != rs2[24,8]); + rd = -4; + if (m1) goto inst_next; + rd = -3; + if (m2) goto inst_next; + rd = -2; + if (m3) goto inst_next; + rd = -1; + if (m4) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1); +@else + m1:1 = (rs1[0,8] != rs2[0,8]); + m2:1 = (rs1[8,8] != rs2[8,8]); + m3:1 = (rs1[16,8] != rs2[16,8]); + m4:1 = (rs1[24,8] != rs2[24,8]); + m5:1 = (rs1[32,8] != rs2[32,8]); + m6:1 = (rs1[40,8] != rs2[40,8]); + m7:1 = (rs1[48,8] != rs2[48,8]); + m8:1 = (rs1[56,8] != rs2[56,8]); + rd = -8; + if (m1) goto inst_next; + rd = -7; + if (m2) goto inst_next; + rd = -6; + if (m3) goto inst_next; + rd = -5; + if (m4) goto inst_next; + rd = -4; + if (m5) goto inst_next; + rd = -3; + if (m6) goto inst_next; + rd = -2; + if (m7) goto inst_next; + rd = -1; + if (m8) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1); +@endif +} + +:flmism rd,rs1,rs2 is rd & rs1 & rs2 & op2531=0b0010011 & op1214=0 & $(CUSTOM2) { +@if XLEN == "4" + m1:1 = (rs1[0,8] != rs2[0,8]); + m2:1 = (rs1[8,8] != rs2[8,8]); + m3:1 = (rs1[16,8] != rs2[16,8]); + m4:1 = (rs1[24,8] != rs2[24,8]); + rd = -1; + if (m4) goto inst_next; + rd = -2; + if (m3) goto inst_next; + rd = -3; + if (m2) goto inst_next; + rd = -4; + if (m1) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-4) + (zext(m2)*-3) + (zext(m3)*-2) + (zext(m4)*-1); +@else + m1:1 = (rs1[0,8] != rs2[0,8]); + m2:1 = (rs1[8,8] != rs2[8,8]); + m3:1 = (rs1[16,8] != rs2[16,8]); + m4:1 = (rs1[24,8] != rs2[24,8]); + m5:1 = (rs1[32,8] != rs2[32,8]); + m6:1 = (rs1[40,8] != rs2[40,8]); + m7:1 = (rs1[48,8] != rs2[48,8]); + m8:1 = (rs1[56,8] != rs2[56,8]); + rd = -1; + if (m8) goto inst_next; + rd = -2; + if (m7) goto inst_next; + rd = -3; + if (m6) goto inst_next; + rd = -4; + if (m5) goto inst_next; + rd = -5; + if (m4) goto inst_next; + rd = -6; + if (m3) goto inst_next; + rd = -7; + if (m2) goto inst_next; + rd = -8; + if (m1) goto inst_next; + rd = 0; + # choosery method + # rd = 0 + (zext(m1)*-8) + (zext(m2)*-7) + (zext(m3)*-6) + (zext(m4)*-5) + (zext(m5)*-4) + (zext(m6)*-3) + (zext(m7)*-2) + (zext(m8)*-1); +@endif +} + +imm11_exec: val is cop1212 & cop1011 & cop0909 & cop0808 & cop0506 & cop0404 & cop0303 & cop0202 + [ val = (cop0808<<11)|(cop1212<<10)|(cop0303<<9)|(cop0909<<8)|(cop0506<<6)|(cop0202<<5)|(cop1011<<3)|(cop0404<<2); ] { + export *[ExecTable]:2 val; +} + +# +# Code Dense (CoDense) extension + + +#100 imm[10|4:3|8] imm[11] 0 imm[7:6|2|9|5] 00 +:exec.it imm11_exec is ecdv=0 & cop1315=4 & imm11_exec & cop0707=0 & cop0001=0 { + ExecRetAddr = inst_next; + goto imm11_exec; +} + +:ex9.it imm11_exec is ecdv=0 & cop1315=4 & imm11_exec & cop0708=0 & cop0001=0 { + ExecRetAddr = inst_next; + goto imm11_exec; +} + +# +# alternate version of EXEC.IT when mmsc_cfb.ECDV=1 +# +imm11_nexec: val is cop1011 & cop0909 & cop0808 & cop0707 & cop0506 & cop0404 & cop0303 & cop0202 + [ val = (cop0808<<11)|(cop0707<<10)|(cop0303<<9)|(cop0909<<8)|(cop0506<<6)|(cop0202<<5)|(cop1011<<3)|(cop0404<<2); ] { + export *[ExecTable]:2 val; +} + +# 100 1 imm[4:3|8] imm[11] imm[10] imm[7:6|2|9|5] 00 +:nexec.it imm11_nexec is ecdv=1 & cop1315=4 & cop1212=1 & imm11_nexec & cop0001=0 { + ExecRetAddr = inst_next; + goto imm11_nexec; +} + +# +# INT4 vector load extension +# +define pcodeop vln8; + +:vln8.v vd,(rs1)^vm is vd & rs1 & op2631=0b000001 & vm & op2024=0b00010 & op1214=0b100 & $(CUSTOM2) { + # TODO load 32 4bit values, possibly sext by vm into 32 8-bit vector registers + val:$(VLEN) = *[ram]:$(VLEN) rs1; + vd = vln8(val); + build vm; +} + +:vlnu8.v vd,(rs1)^vm is vd & rs1 & op2631=0b000001 & vm & op2024=0b00011 & op1214=0b100 & $(CUSTOM2) { + # TODO load 32 4bit values, possibly zext by vm into 32 8-bit vector registers + val:$(VLEN) = *[ram]:$(VLEN) rs1; + vd = vln8(val); + build vm; +} + + +# +# bfloat16 conversion extension +# +define pcodeop fcvt.s.bf16; + +:fcvt.s.bf16 frd,frs2 is frd & frs2 & op2531=0 & op1519=0b00010 & op1214=0b100 & $(CUSTOM2) { + frd = fcvt.s.bf16(frs2); +} + +define pcodeop fcvt.bf16.s; + +:fcvt.bf16.s frd,frs2 is frd & frs2 & op2531=0 & op1519=0b00011 & op1214=0b100 & $(CUSTOM2) { + frd = fcvt.bf16.s(frs2); +} + +# +# Vector BFloat16 conversion extension +# + +define pcodeop vfwcvt.s.bf16; + +:vfwcvt.s.bf16 vd,vs2 is vd & vs2 & op2631=0b000000 & op1519=0b00000 & op1214=0b100 & $(CUSTOM2) { + vd = vfwcvt.s.bf16(vs2); +} + +define pcodeop vfncvt.bf16.s; + +:vfncvt.bf16.s vd,vs2 is vd & vs2 & op2631=0b000000 & op1519=0b00001 & op1214=0b100 & $(CUSTOM2) { + vd = vfncvt.bf16.s(vs2); +} + +define pcodeop vfpmadt.vf; + +:vfpmadt.vf vd,rs1,vs2^vm is vd & rs1 & vs2 & vm & op2631=0b000010 & op1214=0b100 & $(CUSTOM2) { + vd = vfpmadt.vf(rs1,vs2); + build vm; +} + +define pcodeop vfpmadb.vf; + +:vfpmadb.vf vd,rs1,vs2^vm is vd & rs1 & vs2 & vm & op2631=0b000011 & op1214=0b100 & $(CUSTOM2) { + vd = vfpmadb.vf(rs1,vs2); + build vm; +} + +define pcodeop vd4dots.vv; + +:vd4dots.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000100 & op1214=0b100 & $(CUSTOM2) { + vd = vd4dots.vv(vs1,vs2); + build vm; +} + +define pcodeop vd4dotu.vv; + +:vd4dotu.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000111 & op1214=0b100 & $(CUSTOM2) { + vd = vd4dotu.vv(vs1,vs2); + build vm; +} + +define pcodeop vd4dotsu.vv; + +:vd4dotsu.vv vd,vs1,vs2^vm is vd & vs1 & vs2 & vm & op2631=0b000101 & op1214=0b100 & $(CUSTOM2) { + vd = vd4dotsu.vv(vs1,vs2); + build vm; +} + +define pcodeop vle4.v; + +:vle4.v vd,(rs1) is vd & rs1 & op2631=0b000001 & op2525=1 & op2024=0b00000 & op1214=0b100 & $(CUSTOM2) { + val:$(VLEN) = *[ram]:$(VLEN) rs1; + vd = vle4.v(val); +} + +define pcodeop vfwcvt.f.n.v; + +:vfwcvt.f.n.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00100 & op1214=0b100 & $(CUSTOM2) { + vd = vfwcvt.f.n.v(vs2); + build vm; +} + +define pcodeop vfwcvt.f.nu.v; + +:vfwcvt.f.nu.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00101 & op1214=0b100 & $(CUSTOM2) { + vd = vfwcvt.f.nu.v(vs2); + build vm; +} + +define pcodeop vfwcvt.f.b.v; + +:vfwcvt.f.b.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00110 & op1214=0b100 & $(CUSTOM2) { + vd = vfwcvt.f.b.v(vs2); + build vm; +} + +define pcodeop vfwcvt.f.bu.v; + +:vfwcvt.f.bu.v vd,vs2^vm is vd & vs2 & op2631=0b000000 & vm & op1519=0b00111 & op1214=0b100 & $(CUSTOM2) { + vd = vfwcvt.f.bu.v(vs2); + build vm; +} + + diff --git a/pypcode/processors/RISCV/data/languages/andestar_v5.ldefs b/pypcode/processors/RISCV/data/languages/andestar_v5.ldefs new file mode 100644 index 00000000..7d45531b --- /dev/null +++ b/pypcode/processors/RISCV/data/languages/andestar_v5.ldefs @@ -0,0 +1,20 @@ + + + + + + AndeStar v5 RISC-V based 32 little default + + + + + + + diff --git a/pypcode/processors/RISCV/data/languages/andestar_v5.slaspec b/pypcode/processors/RISCV/data/languages/andestar_v5.slaspec new file mode 100644 index 00000000..1720753a --- /dev/null +++ b/pypcode/processors/RISCV/data/languages/andestar_v5.slaspec @@ -0,0 +1,36 @@ +define endian=little; + +@define XLEN 4 +@define XLEN2 8 +@define FLEN 8 +@define CONTEXTLEN 8 + +@define ADDRSIZE "32" +@define FPSIZE "64" + +@include "riscv.reg.sinc" + +define context CONTEXT + isExecInstr=(32,32) + phase=(33,33) + ecdv=(34,34) +; + +@include "riscv.table.sinc" + + +# artificial return register + +define register offset=0x6000 size=4 [ ExecRetAddr ]; + +Dest: is epsilon { export *[ram]:1 ExecRetAddr; } + +:^instruction is phase=0 & isExecInstr=1 & instruction [ phase=1; ] { build instruction; local dest:$(XLEN) = ExecRetAddr; goto [dest]; } +:^instruction is phase=0 & isExecInstr=0 & instruction [ phase=1; ] { build instruction; } + +with : phase=1 { +@include "riscv.instr.sinc" + +@include "andestar_v5.instr.sinc" + +} diff --git a/pypcode/processors/RISCV/data/languages/old/riscv_deprecated.ldefs b/pypcode/processors/RISCV/data/languages/old/riscv_deprecated.ldefs new file mode 100644 index 00000000..0002af5a --- /dev/null +++ b/pypcode/processors/RISCV/data/languages/old/riscv_deprecated.ldefs @@ -0,0 +1,150 @@ + + + + + + RISC-V 64 little base + + + + + + + + RISC-V 64 little base compressed + + + + + + + + RISC-V 64 little general purpose + + + + + + + + RISC-V 64 little general purpose compressed + + + + + + + + RISC-V 32 little base + + + + + + + + RISC-V 32 little base compressed + + + + + + + + RISC-V 32 little base compressed + + + + + + + + RISC-V 32 little general purpose + + + + + + + + RISC-V 32 little general purpose compressed + + + + + + + + \ No newline at end of file diff --git a/pypcode/processors/RISCV/data/languages/riscv.csr.sinc b/pypcode/processors/RISCV/data/languages/riscv.csr.sinc index b29608f2..a38313fe 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.csr.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.csr.sinc @@ -2,71 +2,109 @@ # csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) -:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op1519 +:csrc csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711=0 { local tmprs1:$(XLEN) = rs1; local oldcsr:$(XLEN) = csr:$(XLEN); - rdDst = oldcsr; - local tmp:$(XLEN) = op1519; - if (tmp == 0) goto inst_next; local newcsr:$(XLEN) = oldcsr & ~tmprs1; csr = newcsr; } +# csrrc d,E,s 00003073 0000707f SIMPLE (0, 0) +:csrrc rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x3 & op0711 +{ + local tmprs1:$(XLEN) = rs1; + local oldcsr:$(XLEN) = csr:$(XLEN); + local newcsr:$(XLEN) = oldcsr & ~tmprs1; + csr = newcsr; + rdDst = oldcsr; +} + +# csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) +:csrci csr,op1519 is op1519 & op0711=0 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 +{ + local oldcsr:$(XLEN) = csr:$(XLEN); + local tmp:$(XLEN) = op1519; + csr = oldcsr & ~tmp; +} + # csrrci d,E,Z 00007073 0000707f SIMPLE (0, 0) :csrrci rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x7 { local oldcsr:$(XLEN) = csr:$(XLEN); - rdDst = oldcsr; local tmp:$(XLEN) = op1519; - if (tmp == 0) goto inst_next; - csr = csr & ~tmp; + csr = oldcsr & ~tmp; + rdDst = oldcsr; +} + + +# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) +:csrr rdDst,csr is csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519=0 & op0711 +{ + rdDst = csr:$(XLEN); } +# csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) +:csrs csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711=0 +{ + local oldcsr:$(XLEN) = csr:$(XLEN); + csr = oldcsr | rs1; +} # csrrs d,E,s 00002073 0000707f SIMPLE (0, 0) -:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 +:csrrs rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x2 & op1519 & op0711 { - local tmprs1 = rs1; local oldcsr:$(XLEN) = csr:$(XLEN); - rdDst = oldcsr; - local tmp:$(XLEN) = op1519; - if (tmp == 0) goto inst_next; - csr = csr | tmprs1; + csr = oldcsr | rs1; + rdDst = oldcsr; } +# csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) +:csrsi csr,op1519 is op1519 & csr & op0711=0 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 +{ + local oldcsr:$(XLEN) = csr:$(XLEN); + local tmp:$(XLEN) = op1519; + csr = oldcsr | tmp; +} # csrrsi d,E,Z 00006073 0000707f SIMPLE (0, 0) -:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 +:csrrsi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x6 & op0711 { local oldcsr:$(XLEN) = csr:$(XLEN); - rdDst = oldcsr; local tmp:$(XLEN) = op1519; - if (tmp == 0) goto inst_next; - csr = csr | tmp; + csr = oldcsr | tmp; + rdDst = oldcsr; } +# csrw d,E,s 00001073 0000707f SIMPLE (0, 0) +:csrw csr,rs1 is rs1 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & r0711=0 +{ + csr = rs1; +} # csrrw d,E,s 00001073 0000707f SIMPLE (0, 0) -:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 & op1519 +:csrrw rdDst,csr,rs1 is rs1 & csr & rdDst & r0711 & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x1 { local tmprs1:$(XLEN) = rs1; local oldcsr:$(XLEN) = csr:$(XLEN); - local tmp:$(XLEN) = op1519; csr = tmprs1; - if (tmp == 0) goto inst_next; rdDst = oldcsr; } +# csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) +:csrwi csr,op1519 is op1519 & csr & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711=0 +{ + local val:$(XLEN) = op1519; + csr = val; +} # csrrwi d,E,Z 00005073 0000707f SIMPLE (0, 0) -:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 +:csrrwi rdDst,csr,op1519 is op1519 & csr & rdDst & op0001=0x3 & op0204=0x4 & op0506=0x3 & funct3=0x5 & r0711 { local oldcsr:$(XLEN) = csr:$(XLEN); - local tmp:$(XLEN) = op1519; - csr = tmp; - if (tmp == 0) goto inst_next; + local val:$(XLEN) = op1519; + csr = val; rdDst = oldcsr; } diff --git a/pypcode/processors/RISCV/data/languages/riscv.ilp32d.slaspec b/pypcode/processors/RISCV/data/languages/riscv.ilp32d.slaspec index 81dbf058..ee9976d0 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.ilp32d.slaspec +++ b/pypcode/processors/RISCV/data/languages/riscv.ilp32d.slaspec @@ -4,8 +4,7 @@ define endian=little; @define XLEN2 8 @define FLEN 8 -@define MXLEN_1 31 -@define MXLEN_2 30 +@define CONTEXTLEN 4 @define ADDRSIZE "32" @define FPSIZE "64" @@ -13,3 +12,6 @@ define endian=little; @include "riscv.reg.sinc" @include "riscv.table.sinc" @include "riscv.instr.sinc" + +# include placeholder decode for *some* custom instructions +@include "riscv.custom.sinc" diff --git a/pypcode/processors/RISCV/data/languages/riscv.instr.sinc b/pypcode/processors/RISCV/data/languages/riscv.instr.sinc index 743bdbaf..15a1daa1 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.instr.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.instr.sinc @@ -27,7 +27,6 @@ @include "riscv.rv64m.sinc" @include "riscv.rv64b.sinc" @include "riscv.rv64p.sinc" -@include "riscv.rv64k.sinc" @if FPSIZE == "32" || FPSIZE == "64" || FPSIZE == "128" @include "riscv.rv64f.sinc" @@ -48,8 +47,6 @@ @include "riscv.rvv.sinc" @include "riscv.zi.sinc" -@include "riscv.custom.sinc" - # todos that may be possible, mostly just artifacts from my # script to generate the initial SELIGH diff --git a/pypcode/processors/RISCV/data/languages/riscv.ldefs b/pypcode/processors/RISCV/data/languages/riscv.ldefs index 144a7be1..346f7d6f 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.ldefs +++ b/pypcode/processors/RISCV/data/languages/riscv.ldefs @@ -1,164 +1,30 @@ - - - RISC-V 64 little base - - - - - - - - RISC-V 64 little base compressed - - - - - - - - RISC-V 64 little general purpose - - - - - - - - RISC-V 64 little general purpose compressed - - - - - - + - RISC-V 32 little default + RISC-V 64 little default - - RISC-V 32 little base - - - - - - - - RISC-V 32 little base compressed - - - - - - - - RISC-V 32 little base compressed - - - - - - - - RISC-V 32 little general purpose - - - - - - - - RISC-V 32 little general purpose compressed - - - - - - + RISC-V 32 little default @@ -167,5 +33,5 @@ - + diff --git a/pypcode/processors/RISCV/data/languages/riscv.lp64d.slaspec b/pypcode/processors/RISCV/data/languages/riscv.lp64d.slaspec index c07b5382..f1d11a23 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.lp64d.slaspec +++ b/pypcode/processors/RISCV/data/languages/riscv.lp64d.slaspec @@ -4,8 +4,7 @@ define endian=little; @define XLEN2 16 @define FLEN 8 -@define MXLEN_1 63 -@define MXLEN_2 62 +@define CONTEXTLEN 4 @define ADDRSIZE "64" @define FPSIZE "64" @@ -13,3 +12,6 @@ define endian=little; @include "riscv.reg.sinc" @include "riscv.table.sinc" @include "riscv.instr.sinc" + +@include "riscv.rv64k.sinc" # current encoding is in custom space +@include "riscv.custom.sinc" diff --git a/pypcode/processors/RISCV/data/languages/riscv.opinion b/pypcode/processors/RISCV/data/languages/riscv.opinion index 4f550ded..dee07a29 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.opinion +++ b/pypcode/processors/RISCV/data/languages/riscv.opinion @@ -11,18 +11,11 @@ - - - - - - - - - - - - + + + + + diff --git a/pypcode/processors/RISCV/data/languages/riscv.reg.sinc b/pypcode/processors/RISCV/data/languages/riscv.reg.sinc index 5b09d07e..ecd02ef3 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.reg.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.reg.sinc @@ -4,6 +4,10 @@ define alignment=2; define space ram type=ram_space size=$(XLEN) default; define space register type=register_space size=4; +define space csreg type=ram_space size=2 wordsize=$(XLEN); # really 12bit space, for 4096 registers + +define register offset=0x100 size=$(CONTEXTLEN) [ CONTEXT ]; + define register offset=0x1000 size=$(XLEN) [ pc ]; @@ -51,530 +55,14 @@ define register offset=0x3000 size=$(FLEN) [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; #TODO fix -@define VLEN "256" +@define VLEN "32" define register offset=0x4000 size=$(VLEN) [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ]; - -define register offset=0x90000000 size=$(XLEN) [ - ustatus fflags frm fcsr uie utvec csr006 csr007 - vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr - csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017 - csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f - csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027 - csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f - csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037 - csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f - uscratch uepc ucause utval uip csr045 csr046 csr047 - csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f - csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057 - csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f - csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067 - csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f - csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077 - csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f - csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087 - csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f - csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097 - csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f - csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7 - csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af - csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7 - csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf - csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7 - csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf - csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7 - csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df - csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7 - csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef - csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7 - csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff - sstatus csr101 sedeleg sideleg sie stvec scounteren csr107 - csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f - csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117 - csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f - csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 - csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f - csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137 - csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f - sscratch sepc scause stval sip csr145 csr146 csr147 - csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f - csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157 - csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f - csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 - csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f - csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177 - csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f - satp csr181 csr182 csr183 csr184 csr185 csr186 csr187 - csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f - csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197 - csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f - csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7 - csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af - csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7 - csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf - csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7 - csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf - csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7 - csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df - csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7 - csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef - csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7 - csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff - vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207 - csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f - csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217 - csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f - csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227 - csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f - csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237 - csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f - vsscratch vsepc vscause vstval vsip csr245 csr246 csr247 - csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f - csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257 - csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f - csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267 - csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f - csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277 - csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f - vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287 - csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f - csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297 - csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f - csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7 - csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af - csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7 - csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf - csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7 - csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf - csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7 - csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df - csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7 - csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef - csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7 - csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff - mstatus misa medeleg mideleg mie mtvec mcounteren csr307 - csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f - mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317 - csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f - mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 - mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15 - mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 - mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31 - mscratch mepc mcause mtval mip csr345 csr346 csr347 - csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f - csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357 - csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f - csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367 - csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f - csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377 - csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f - mbase mbound mibase mibound mdbase mdbound csr386 csr387 - csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f - csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397 - csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f - pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7 - pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15 - pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 - pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15 - pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23 - pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31 - pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39 - pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47 - pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55 - pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63 - csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7 - csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff - csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407 - csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f - csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417 - csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f - csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427 - csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f - csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437 - csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f - csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447 - csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f - csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457 - csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f - csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467 - csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f - csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477 - csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f - csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487 - csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f - csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497 - csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f - csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7 - csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af - csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7 - csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf - csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7 - csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf - csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7 - csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df - csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7 - csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef - csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7 - csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff - csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507 - csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f - csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517 - csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f - csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527 - csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f - csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537 - csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f - csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547 - csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f - csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557 - csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f - csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567 - csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f - csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577 - csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f - csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587 - csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f - csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597 - csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f - csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7 - scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af - csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7 - csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf - csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7 - csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf - csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7 - csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df - csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7 - csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef - csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7 - csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff - hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie - csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f - csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617 - csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f - csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627 - csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f - csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637 - csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f - csr640 csr641 csr642 htval hip hvip csr646 csr647 - csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f - csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657 - csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f - csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667 - csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f - csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677 - csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f - hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687 - csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f - csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697 - csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f - csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7 - hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af - csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7 - csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf - csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7 - csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf - csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7 - csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df - csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7 - csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef - csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7 - csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff - csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707 - csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f - csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717 - csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f - csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727 - csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f - csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737 - csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f - csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747 - csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f - csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757 - csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f - csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767 - csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f - csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777 - csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f - csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787 - csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f - csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797 - csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f - tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7 - mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af - dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7 - csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf - csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7 - csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf - csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7 - csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df - csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7 - csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef - csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7 - csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff - csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807 - csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f - csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817 - csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f - csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827 - csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f - csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837 - csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f - csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847 - csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f - csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857 - csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f - csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867 - csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f - csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877 - csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f - csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887 - csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f - csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897 - csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f - csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7 - csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af - csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7 - csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf - csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7 - csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf - csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7 - csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df - csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7 - csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef - csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7 - csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff - csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907 - csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f - csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917 - csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f - csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927 - csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f - csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937 - csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f - csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947 - csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f - csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957 - csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f - csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967 - csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f - csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977 - csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f - csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987 - csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f - csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997 - csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f - csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7 - csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af - csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7 - csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf - csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7 - csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf - csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7 - csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df - csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7 - csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef - csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7 - csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff - csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07 - csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f - csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17 - csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f - csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27 - csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f - csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37 - csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f - csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47 - csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f - csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57 - csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f - csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67 - csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f - csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77 - csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f - csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87 - csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f - csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97 - csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f - csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7 - csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf - csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7 - csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf - csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7 - csrac8 csrac9 csraca csracb csracc csracd csrace csracf - csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7 - csrad8 csrad9 csrada csradb csradc csradd csrade csradf - csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7 - csrae8 csrae9 csraea csraeb csraec csraed csraee csraef - csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7 - csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff - mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7 - mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15 - mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23 - mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31 - csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27 - csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f - csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37 - csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f - csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47 - csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f - csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57 - csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f - csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67 - csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f - csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77 - csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f - mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h - mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h - mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h - mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h - csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7 - csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf - csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7 - csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf - csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7 - csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf - csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7 - csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf - csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7 - csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef - csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7 - csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff - cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7 - hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15 - hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23 - hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31 - vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27 - csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f - csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37 - csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f - csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47 - csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f - csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57 - csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f - csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67 - csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f - csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77 - csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f - cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h - hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h - hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h - hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h - csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7 - csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf - csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7 - csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf - csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7 - csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf - csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7 - csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf - csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7 - csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef - csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7 - csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff - csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07 - csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f - csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17 - csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f - csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27 - csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f - csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37 - csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f - csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47 - csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f - csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57 - csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f - csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67 - csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f - csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77 - csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f - csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87 - csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f - csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97 - csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f - csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7 - csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf - csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7 - csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf - csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7 - csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf - csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7 - csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf - csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7 - csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef - csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7 - csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff - csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07 - csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f - csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17 - csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f - csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27 - csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f - csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37 - csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f - csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47 - csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f - csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57 - csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f - csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67 - csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f - csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77 - csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f - csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87 - csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f - csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97 - csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f - csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7 - csrea8 csrea9 csreaa csreab csreac csread csreae csreaf - csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7 - csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf - csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7 - csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf - csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7 - csred8 csred9 csreda csredb csredc csredd csrede csredf - csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7 - csree8 csree9 csreea csreeb csreec csreed csreee csreef - csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7 - csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff - csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07 - csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f - csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17 - csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f - csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27 - csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f - csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37 - csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f - csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47 - csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f - csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57 - csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f - csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67 - csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f - csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77 - csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f - csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87 - csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f - csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97 - csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f - csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7 - csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf - csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7 - csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf - csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7 - csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf - csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7 - csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf - csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7 - csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef - csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7 - csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff -]; - - -# SEE 3.1.1 Machine ISA Register misa + + # SEE 3.1.1 Machine ISA Register misa # (MXLEN-1, MXLEN-2) MXL - Machine XLEN {1: 32, 2: 64, 3: 128} # Bit Character Description # 0 A Atomic extension @@ -603,34 +91,1056 @@ define register offset=0x90000000 size=$(XLEN) [ # 23 X Non-standard extensions present # 24 Y Reserved # 25 Z Reserved -define context misa - RVA=(0,0) - RVB=(1,1) - RVC=(2,2) - RVD=(3,3) - RVE=(4,4) - RVF=(5,5) - RVG=(6,6) - RVH=(7,7) - RVI=(8,8) - RVJ=(9,9) - RVK=(10,10) - RVL=(11,11) - RVM=(12,12) - RVN=(13,13) - RVO=(14,14) - RVP=(15,15) - RVQ=(16,16) - RVR=(17,17) - RVS=(18,18) - RVT=(19,19) - RVU=(20,20) - RVV=(21,21) - RVW=(22,22) - RVX=(23,23) - RVY=(24,24) - RVZ=(25,25) - MXL=($(MXLEN_2), $(MXLEN_1)) + + +# Moved most CSR registers to .pspec file. Doing so will: +# - Allow new registers to be named in the .pspec file +# - Processor variants differing only in CSR registers can just use a variant.pspec +# - Read/Write references to registers not defined in sleigh +# - Registers defined here will not get references to them +# - Allow rename and comment by end user + +# +# Control registers reserved 0x0000-0x0fff +@define CSR_REG_START "0x0000" + +## CSR definitions is done as a big table with undefined holes so that +## the 32-bit and 64-bit tables can be defined with the same code. +## Otherwise the byte offset of the address of each register +## would need to be calculated and would be different for XLEN of 32 or 64 bit. +define csreg offset=$(CSR_REG_START) size=$(XLEN) [ +# 0x000 + _ fflags frm fcsr _ _ _ _ +# 0x008 + _ _ _ _ _ _ _ _ +# 0x010 + _ _ _ _ _ _ _ _ +# 0x018 + _ _ _ _ _ _ _ _ +# 0x020 + _ _ _ _ _ _ _ _ +# 0x028 + _ _ _ _ _ _ _ _ +# 0x030 + _ _ _ _ _ _ _ _ +# 0x038 + _ _ _ _ _ _ _ _ +# 0x040 + _ uepc _ _ _ _ _ _ +# 0x048 + _ _ _ _ _ _ _ _ +# 0x050 + _ _ _ _ _ _ _ _ +# 0x058 + _ _ _ _ _ _ _ _ +# 0x060 + _ _ _ _ _ _ _ _ +# 0x068 + _ _ _ _ _ _ _ _ +# 0x070 + _ _ _ _ _ _ _ _ +# 0x078 + _ _ _ _ _ _ _ _ +# 0x080 + _ _ _ _ _ _ _ _ +# 0x088 + _ _ _ _ _ _ _ _ +# 0x090 + _ _ _ _ _ _ _ _ +# 0x098 + _ _ _ _ _ _ _ _ +# 0x0a0 + _ _ _ _ _ _ _ _ +# 0x0a8 + _ _ _ _ _ _ _ _ +# 0x0b0 + _ _ _ _ _ _ _ _ +# 0x0b8 + _ _ _ _ _ _ _ _ +# 0x0c0 + _ _ _ _ _ _ _ _ +# 0x0c8 + _ _ _ _ _ _ _ _ +# 0x0d0 + _ _ _ _ _ _ _ _ +# 0x0d8 + _ _ _ _ _ _ _ _ +# 0x0e0 + _ _ _ _ _ _ _ _ +# 0x0e8 + _ _ _ _ _ _ _ _ +# 0x0f0 + _ _ _ _ _ _ _ _ +# 0x0f8 + _ _ _ _ _ _ _ _ +# 0x100 + _ _ _ _ _ _ _ _ +# 0x108 + _ _ _ _ _ _ _ _ +# 0x110 + _ _ _ _ _ _ _ _ +# 0x118 + _ _ _ _ _ _ _ _ +# 0x120 + _ _ _ _ _ _ _ _ +# 0x128 + _ _ _ _ _ _ _ _ +# 0x130 + _ _ _ _ _ _ _ _ +# 0x138 + _ _ _ _ _ _ _ _ +# 0x140 + _ sepc _ _ _ _ _ _ +# 0x148 + _ _ _ _ _ _ _ _ +# 0x150 + _ _ _ _ _ _ _ _ +# 0x158 + _ _ _ _ _ _ _ _ +# 0x160 + _ _ _ _ _ _ _ _ +# 0x168 + _ _ _ _ _ _ _ _ +# 0x170 + _ _ _ _ _ _ _ _ +# 0x178 + _ _ _ _ _ _ _ _ +# 0x180 + _ _ _ _ _ _ _ _ +# 0x188 + _ _ _ _ _ _ _ _ +# 0x190 + _ _ _ _ _ _ _ _ +# 0x198 + _ _ _ _ _ _ _ _ +# 0x1a0 + _ _ _ _ _ _ _ _ +# 0x1a8 + _ _ _ _ _ _ _ _ +# 0x1b0 + _ _ _ _ _ _ _ _ +# 0x1b8 + _ _ _ _ _ _ _ _ +# 0x1c0 + _ _ _ _ _ _ _ _ +# 0x1c8 + _ _ _ _ _ _ _ _ +# 0x1d0 + _ _ _ _ _ _ _ _ +# 0x1d8 + _ _ _ _ _ _ _ _ +# 0x1e0 + _ _ _ _ _ _ _ _ +# 0x1e8 + _ _ _ _ _ _ _ _ +# 0x1f0 + _ _ _ _ _ _ _ _ +# 0x1f8 + _ _ _ _ _ _ _ _ +# 0x200 + _ _ _ _ _ _ _ _ +# 0x208 + _ _ _ _ _ _ _ _ +# 0x210 + _ _ _ _ _ _ _ _ +# 0x218 + _ _ _ _ _ _ _ _ +# 0x220 + _ _ _ _ _ _ _ _ +# 0x228 + _ _ _ _ _ _ _ _ +# 0x230 + _ _ _ _ _ _ _ _ +# 0x238 + _ _ _ _ _ _ _ _ +# 0x240 + _ _ _ _ _ _ _ _ +# 0x248 + _ _ _ _ _ _ _ _ +# 0x250 + _ _ _ _ _ _ _ _ +# 0x258 + _ _ _ _ _ _ _ _ +# 0x260 + _ _ _ _ _ _ _ _ +# 0x268 + _ _ _ _ _ _ _ _ +# 0x270 + _ _ _ _ _ _ _ _ +# 0x278 + _ _ _ _ _ _ _ _ +# 0x280 + _ _ _ _ _ _ _ _ +# 0x288 + _ _ _ _ _ _ _ _ +# 0x290 + _ _ _ _ _ _ _ _ +# 0x298 + _ _ _ _ _ _ _ _ +# 0x2a0 + _ _ _ _ _ _ _ _ +# 0x2a8 + _ _ _ _ _ _ _ _ +# 0x2b0 + _ _ _ _ _ _ _ _ +# 0x2b8 + _ _ _ _ _ _ _ _ +# 0x2c0 + _ _ _ _ _ _ _ _ +# 0x2c8 + _ _ _ _ _ _ _ _ +# 0x2d0 + _ _ _ _ _ _ _ _ +# 0x2d8 + _ _ _ _ _ _ _ _ +# 0x2e0 + _ _ _ _ _ _ _ _ +# 0x2e8 + _ _ _ _ _ _ _ _ +# 0x2f0 + _ _ _ _ _ _ _ _ +# 0x2f8 + _ _ _ _ _ _ _ _ +# 0x310 + _ _ _ _ _ _ _ _ +# 0x308 + _ _ _ _ _ _ _ _ +# 0x310 + _ _ _ _ _ _ _ _ +# 0x318 + _ _ _ _ _ _ _ _ +# 0x320 + _ _ _ _ _ _ _ _ +# 0x328 + _ _ _ _ _ _ _ _ +# 0x330 + _ _ _ _ _ _ _ _ +# 0x338 + _ _ _ _ _ _ _ _ +# 0x318 + _ mepc _ _ _ _ _ _ +# 0x348 + _ _ _ _ _ _ _ _ +# 0x350 + _ _ _ _ _ _ _ _ +# 0x358 + _ _ _ _ _ _ _ _ +# 0x360 + _ _ _ _ _ _ _ _ +# 0x368 + _ _ _ _ _ _ _ _ +# 0x370 + _ _ _ _ _ _ _ _ +# 0x378 + _ _ _ _ _ _ _ _ +# 0x380 + _ _ _ _ _ _ _ _ +# 0x388 + _ _ _ _ _ _ _ _ +# 0x390 + _ _ _ _ _ _ _ _ +# 0x398 + _ _ _ _ _ _ _ _ +# 0x3a0 + _ _ _ _ _ _ _ _ +# 0x3a8 + _ _ _ _ _ _ _ _ +# 0x3b0 + _ _ _ _ _ _ _ _ +# 0x3b8 + _ _ _ _ _ _ _ _ +# 0x3c0 + _ _ _ _ _ _ _ _ +# 0x3c8 + _ _ _ _ _ _ _ _ +# 0x3d0 + _ _ _ _ _ _ _ _ +# 0x3d8 + _ _ _ _ _ _ _ _ +# 0x3e0 + _ _ _ _ _ _ _ _ +# 0x3e8 + _ _ _ _ _ _ _ _ +# 0x3f0 + _ _ _ _ _ _ _ _ +# 0x3f8 + _ _ _ _ _ _ _ _ +# 0x400 + _ _ _ _ _ _ _ _ +# 0x408 + _ _ _ _ _ _ _ _ +# 0x410 + _ _ _ _ _ _ _ _ +# 0x418 + _ _ _ _ _ _ _ _ +# 0x420 + _ _ _ _ _ _ _ _ +# 0x428 + _ _ _ _ _ _ _ _ +# 0x430 + _ _ _ _ _ _ _ _ +# 0x438 + _ _ _ _ _ _ _ _ +# 0x440 + _ _ _ _ _ _ _ _ +# 0x448 + _ _ _ _ _ _ _ _ +# 0x450 + _ _ _ _ _ _ _ _ +# 0x458 + _ _ _ _ _ _ _ _ +# 0x460 + _ _ _ _ _ _ _ _ +# 0x468 + _ _ _ _ _ _ _ _ +# 0x470 + _ _ _ _ _ _ _ _ +# 0x478 + _ _ _ _ _ _ _ _ +# 0x480 + _ _ _ _ _ _ _ _ +# 0x488 + _ _ _ _ _ _ _ _ +# 0x490 + _ _ _ _ _ _ _ _ +# 0x498 + _ _ _ _ _ _ _ _ +# 0x4a0 + _ _ _ _ _ _ _ _ +# 0x4a8 + _ _ _ _ _ _ _ _ +# 0x4b0 + _ _ _ _ _ _ _ _ +# 0x4b8 + _ _ _ _ _ _ _ _ +# 0x4c0 + _ _ _ _ _ _ _ _ +# 0x4c8 + _ _ _ _ _ _ _ _ +# 0x4d0 + _ _ _ _ _ _ _ _ +# 0x4d8 + _ _ _ _ _ _ _ _ +# 0x4e0 + _ _ _ _ _ _ _ _ +# 0x4e8 + _ _ _ _ _ _ _ _ +# 0x4f0 + _ _ _ _ _ _ _ _ +# 0x4f8 + _ _ _ _ _ _ _ _ +# 0x500 + _ _ _ _ _ _ _ _ +# 0x508 + _ _ _ _ _ _ _ _ +# 0x510 + _ _ _ _ _ _ _ _ +# 0x518 + _ _ _ _ _ _ _ _ +# 0x520 + _ _ _ _ _ _ _ _ +# 0x528 + _ _ _ _ _ _ _ _ +# 0x530 + _ _ _ _ _ _ _ _ +# 0x538 + _ _ _ _ _ _ _ _ +# 0x540 + _ _ _ _ _ _ _ _ +# 0x548 + _ _ _ _ _ _ _ _ +# 0x550 + _ _ _ _ _ _ _ _ +# 0x558 + _ _ _ _ _ _ _ _ +# 0x560 + _ _ _ _ _ _ _ _ +# 0x568 + _ _ _ _ _ _ _ _ +# 0x570 + _ _ _ _ _ _ _ _ +# 0x578 + _ _ _ _ _ _ _ _ +# 0x580 + _ _ _ _ _ _ _ _ +# 0x588 + _ _ _ _ _ _ _ _ +# 0x590 + _ _ _ _ _ _ _ _ +# 0x598 + _ _ _ _ _ _ _ _ +# 0x5a0 + _ _ _ _ _ _ _ _ +# 0x5a8 + _ _ _ _ _ _ _ _ +# 0x5b0 + _ _ _ _ _ _ _ _ +# 0x5b8 + _ _ _ _ _ _ _ _ +# 0x5c0 + _ _ _ _ _ _ _ _ +# 0x5c8 + _ _ _ _ _ _ _ _ +# 0x5d0 + _ _ _ _ _ _ _ _ +# 0x5d8 + _ _ _ _ _ _ _ _ +# 0x5e0 + _ _ _ _ _ _ _ _ +# 0x5e8 + _ _ _ _ _ _ _ _ +# 0x5f0 + _ _ _ _ _ _ _ _ +# 0x5f8 + _ _ _ _ _ _ _ _ +# 0x600 + _ _ _ _ _ _ _ _ +# 0x608 + _ _ _ _ _ _ _ _ +# 0x610 + _ _ _ _ _ _ _ _ +# 0x618 + _ _ _ _ _ _ _ _ +# 0x620 + _ _ _ _ _ _ _ _ +# 0x628 + _ _ _ _ _ _ _ _ +# 0x630 + _ _ _ _ _ _ _ _ +# 0x638 + _ _ _ _ _ _ _ _ +# 0x640 + _ _ _ _ _ _ _ _ +# 0x648 + _ _ _ _ _ _ _ _ +# 0x650 + _ _ _ _ _ _ _ _ +# 0x658 + _ _ _ _ _ _ _ _ +# 0x660 + _ _ _ _ _ _ _ _ +# 0x668 + _ _ _ _ _ _ _ _ +# 0x670 + _ _ _ _ _ _ _ _ +# 0x678 + _ _ _ _ _ _ _ _ +# 0x680 + _ _ _ _ _ _ _ _ +# 0x688 + _ _ _ _ _ _ _ _ +# 0x690 + _ _ _ _ _ _ _ _ +# 0x698 + _ _ _ _ _ _ _ _ +# 0x6a0 + _ _ _ _ _ _ _ _ +# 0x6a8 + _ _ _ _ _ _ _ _ +# 0x6b0 + _ _ _ _ _ _ _ _ +# 0x6b8 + _ _ _ _ _ _ _ _ +# 0x6c0 + _ _ _ _ _ _ _ _ +# 0x6c8 + _ _ _ _ _ _ _ _ +# 0x6d0 + _ _ _ _ _ _ _ _ +# 0x6d8 + _ _ _ _ _ _ _ _ +# 0x6e0 + _ _ _ _ _ _ _ _ +# 0x6e8 + _ _ _ _ _ _ _ _ +# 0x6f0 + _ _ _ _ _ _ _ _ +# 0x6f8 + _ _ _ _ _ _ _ _ +# 0x700 + _ _ _ _ _ _ _ _ +# 0x708 + _ _ _ _ _ _ _ _ +# 0x710 + _ _ _ _ _ _ _ _ +# 0x718 + _ _ _ _ _ _ _ _ +# 0x720 + _ _ _ _ _ _ _ _ +# 0x728 + _ _ _ _ _ _ _ _ +# 0x730 + _ _ _ _ _ _ _ _ +# 0x738 + _ _ _ _ _ _ _ _ +# 0x740 + _ _ _ _ _ _ _ _ +# 0x748 + _ _ _ _ _ _ _ _ +# 0x750 + _ _ _ _ _ _ _ _ +# 0x758 + _ _ _ _ _ _ _ _ +# 0x760 + _ _ _ _ _ _ _ _ +# 0x768 + _ _ _ _ _ _ _ _ +# 0x770 + _ _ _ _ _ _ _ _ +# 0x778 + _ _ _ _ _ _ _ _ +# 0x780 + _ _ _ _ _ _ _ _ +# 0x788 + _ _ _ _ _ _ _ _ +# 0x790 + _ _ _ _ _ _ _ _ +# 0x798 + _ _ _ _ _ _ _ _ +# 0x7a0 + _ _ _ _ _ _ _ _ +# 0x7a8 + _ _ _ _ _ _ _ _ +# 0x7b0 + dcsr dpc dscratch0 dscratch1 _ _ _ _ +# 0x7b8 + _ _ _ _ _ _ _ _ +# 0x7c0 + _ _ _ _ _ _ _ _ +# 0x7c8 + _ _ _ _ _ _ _ _ +# 0x7d0 + _ _ _ _ _ _ _ _ +# 0x7d8 + _ _ _ _ _ _ _ _ +# 0x7e0 + _ _ _ _ _ _ _ _ +# 0x7e8 + _ _ _ _ _ _ _ _ +# 0x7f0 + _ _ _ _ _ _ _ _ +# 0x7f8 + _ _ _ _ _ _ _ _ +# 0x800 + _ _ _ _ _ _ _ _ +# 0x808 + _ _ _ _ _ _ _ _ +# 0x810 + _ _ _ _ _ _ _ _ +# 0x818 + _ _ _ _ _ _ _ _ +# 0x820 + _ _ _ _ _ _ _ _ +# 0x828 + _ _ _ _ _ _ _ _ +# 0x830 + _ _ _ _ _ _ _ _ +# 0x838 + _ _ _ _ _ _ _ _ +# 0x840 + _ _ _ _ _ _ _ _ +# 0x848 + _ _ _ _ _ _ _ _ +# 0x850 + _ _ _ _ _ _ _ _ +# 0x858 + _ _ _ _ _ _ _ _ +# 0x860 + _ _ _ _ _ _ _ _ +# 0x868 + _ _ _ _ _ _ _ _ +# 0x870 + _ _ _ _ _ _ _ _ +# 0x878 + _ _ _ _ _ _ _ _ +# 0x880 + _ _ _ _ _ _ _ _ +# 0x888 + _ _ _ _ _ _ _ _ +# 0x890 + _ _ _ _ _ _ _ _ +# 0x898 + _ _ _ _ _ _ _ _ +# 0x8a0 + _ _ _ _ _ _ _ _ +# 0x8a8 + _ _ _ _ _ _ _ _ +# 0x8b0 + _ _ _ _ _ _ _ _ +# 0x8b8 + _ _ _ _ _ _ _ _ +# 0x8c0 + _ _ _ _ _ _ _ _ +# 0x8c8 + _ _ _ _ _ _ _ _ +# 0x8d0 + _ _ _ _ _ _ _ _ +# 0x8d8 + _ _ _ _ _ _ _ _ +# 0x8e0 + _ _ _ _ _ _ _ _ +# 0x8e8 + _ _ _ _ _ _ _ _ +# 0x8f0 + _ _ _ _ _ _ _ _ +# 0x8f8 + _ _ _ _ _ _ _ _ +# 0x900 + _ _ _ _ _ _ _ _ +# 0x908 + _ _ _ _ _ _ _ _ +# 0x910 + _ _ _ _ _ _ _ _ +# 0x918 + _ _ _ _ _ _ _ _ +# 0x920 + _ _ _ _ _ _ _ _ +# 0x928 + _ _ _ _ _ _ _ _ +# 0x930 + _ _ _ _ _ _ _ _ +# 0x938 + _ _ _ _ _ _ _ _ +# 0x940 + _ _ _ _ _ _ _ _ +# 0x948 + _ _ _ _ _ _ _ _ +# 0x950 + _ _ _ _ _ _ _ _ +# 0x958 + _ _ _ _ _ _ _ _ +# 0x960 + _ _ _ _ _ _ _ _ +# 0x968 + _ _ _ _ _ _ _ _ +# 0x970 + _ _ _ _ _ _ _ _ +# 0x978 + _ _ _ _ _ _ _ _ +# 0x980 + _ _ _ _ _ _ _ _ +# 0x988 + _ _ _ _ _ _ _ _ +# 0x990 + _ _ _ _ _ _ _ _ +# 0x998 + _ _ _ _ _ _ _ _ +# 0x9a0 + _ _ _ _ _ _ _ _ +# 0x9a8 + _ _ _ _ _ _ _ _ +# 0x9b0 + _ _ _ _ _ _ _ _ +# 0x9b8 + _ _ _ _ _ _ _ _ +# 0x9c0 + _ _ _ _ _ _ _ _ +# 0x9c8 + _ _ _ _ _ _ _ _ +# 0x9d0 + _ _ _ _ _ _ _ _ +# 0x9d8 + _ _ _ _ _ _ _ _ +# 0x9e0 + _ _ _ _ _ _ _ _ +# 0x9e8 + _ _ _ _ _ _ _ _ +# 0x9f0 + _ _ _ _ _ _ _ _ +# 0x9f8 + _ _ _ _ _ _ _ _ +# 0xa00 + _ _ _ _ _ _ _ _ +# 0xa08 + _ _ _ _ _ _ _ _ +# 0xa10 + _ _ _ _ _ _ _ _ +# 0xa18 + _ _ _ _ _ _ _ _ +# 0xa20 + _ _ _ _ _ _ _ _ +# 0xa28 + _ _ _ _ _ _ _ _ +# 0xa30 + _ _ _ _ _ _ _ _ +# 0xa38 + _ _ _ _ _ _ _ _ +# 0xa40 + _ _ _ _ _ _ _ _ +# 0xa48 + _ _ _ _ _ _ _ _ +# 0xa50 + _ _ _ _ _ _ _ _ +# 0xa58 + _ _ _ _ _ _ _ _ +# 0xa60 + _ _ _ _ _ _ _ _ +# 0xa68 + _ _ _ _ _ _ _ _ +# 0xa70 + _ _ _ _ _ _ _ _ +# 0xa78 + _ _ _ _ _ _ _ _ +# 0xa80 + _ _ _ _ _ _ _ _ +# 0xa88 + _ _ _ _ _ _ _ _ +# 0xa90 + _ _ _ _ _ _ _ _ +# 0xa98 + _ _ _ _ _ _ _ _ +# 0xaa0 + _ _ _ _ _ _ _ _ +# 0xaa8 + _ _ _ _ _ _ _ _ +# 0xab0 + _ _ _ _ _ _ _ _ +# 0xab8 + _ _ _ _ _ _ _ _ +# 0xac0 + _ _ _ _ _ _ _ _ +# 0xac8 + _ _ _ _ _ _ _ _ +# 0xad0 + _ _ _ _ _ _ _ _ +# 0xad8 + _ _ _ _ _ _ _ _ +# 0xae0 + _ _ _ _ _ _ _ _ +# 0xae8 + _ _ _ _ _ _ _ _ +# 0xaf0 + _ _ _ _ _ _ _ _ +# 0xaf8 + _ _ _ _ _ _ _ _ +# 0xa00 + _ _ _ _ _ _ _ _ +# 0xa08 + _ _ _ _ _ _ _ _ +# 0xa10 + _ _ _ _ _ _ _ _ +# 0xa18 + _ _ _ _ _ _ _ _ +# 0xb20 + _ _ _ _ _ _ _ _ +# 0xb28 + _ _ _ _ _ _ _ _ +# 0xb30 + _ _ _ _ _ _ _ _ +# 0xb38 + _ _ _ _ _ _ _ _ +# 0xb40 + _ _ _ _ _ _ _ _ +# 0xb48 + _ _ _ _ _ _ _ _ +# 0xb50 + _ _ _ _ _ _ _ _ +# 0xb58 + _ _ _ _ _ _ _ _ +# 0xb60 + _ _ _ _ _ _ _ _ +# 0xb68 + _ _ _ _ _ _ _ _ +# 0xb70 + _ _ _ _ _ _ _ _ +# 0xb78 + _ _ _ _ _ _ _ _ +# 0xb80 + _ _ _ _ _ _ _ _ +# 0xb88 + _ _ _ _ _ _ _ _ +# 0xb90 + _ _ _ _ _ _ _ _ +# 0xb98 + _ _ _ _ _ _ _ _ +# 0xba0 + _ _ _ _ _ _ _ _ +# 0xba8 + _ _ _ _ _ _ _ _ +# 0xbb0 + _ _ _ _ _ _ _ _ +# 0xbb8 + _ _ _ _ _ _ _ _ +# 0xbc0 + _ _ _ _ _ _ _ _ +# 0xbc8 + _ _ _ _ _ _ _ _ +# 0xbd0 + _ _ _ _ _ _ _ _ +# 0xbd8 + _ _ _ _ _ _ _ _ +# 0xbe0 + _ _ _ _ _ _ _ _ +# 0xbe8 + _ _ _ _ _ _ _ _ +# 0xbf0 + _ _ _ _ _ _ _ _ +# 0xbf8 + _ _ _ _ _ _ _ _ +# 0xc00 + _ _ _ _ _ _ _ _ +# 0xc08 + _ _ _ _ _ _ _ _ +# 0xc10 + _ _ _ _ _ _ _ _ +# 0xc18 + _ _ _ _ _ _ _ _ +# 0xc20 + _ _ _ _ _ _ _ _ +# 0xc28 + _ _ _ _ _ _ _ _ +# 0xc30 + _ _ _ _ _ _ _ _ +# 0xc38 + _ _ _ _ _ _ _ _ +# 0xc40 + _ _ _ _ _ _ _ _ +# 0xc48 + _ _ _ _ _ _ _ _ +# 0xc50 + _ _ _ _ _ _ _ _ +# 0xc58 + _ _ _ _ _ _ _ _ +# 0xc60 + _ _ _ _ _ _ _ _ +# 0xc68 + _ _ _ _ _ _ _ _ +# 0xc70 + _ _ _ _ _ _ _ _ +# 0xc78 + _ _ _ _ _ _ _ _ +# 0xc80 + _ _ _ _ _ _ _ _ +# 0xc88 + _ _ _ _ _ _ _ _ +# 0xc90 + _ _ _ _ _ _ _ _ +# 0xc98 + _ _ _ _ _ _ _ _ +# 0xca0 + _ _ _ _ _ _ _ _ +# 0xca8 + _ _ _ _ _ _ _ _ +# 0xcb0 + _ _ _ _ _ _ _ _ +# 0xcb8 + _ _ _ _ _ _ _ _ +# 0xcc0 + _ _ _ _ _ _ _ _ +# 0xcc8 + _ _ _ _ _ _ _ _ +# 0xcd0 + _ _ _ _ _ _ _ _ +# 0xcd8 + _ _ _ _ _ _ _ _ +# 0xce0 + _ _ _ _ _ _ _ _ +# 0xce8 + _ _ _ _ _ _ _ _ +# 0xcf0 + _ _ _ _ _ _ _ _ +# 0xcf8 + _ _ _ _ _ _ _ _ +# 0xd00 + _ _ _ _ _ _ _ _ +# 0xd08 + _ _ _ _ _ _ _ _ +# 0xd10 + _ _ _ _ _ _ _ _ +# 0xd18 + _ _ _ _ _ _ _ _ +# 0xd20 + _ _ _ _ _ _ _ _ +# 0xd28 + _ _ _ _ _ _ _ _ +# 0xd30 + _ _ _ _ _ _ _ _ +# 0xd38 + _ _ _ _ _ _ _ _ +# 0xd40 + _ _ _ _ _ _ _ _ +# 0xd48 + _ _ _ _ _ _ _ _ +# 0xd50 + _ _ _ _ _ _ _ _ +# 0xd58 + _ _ _ _ _ _ _ _ +# 0xd60 + _ _ _ _ _ _ _ _ +# 0xd68 + _ _ _ _ _ _ _ _ +# 0xd70 + _ _ _ _ _ _ _ _ +# 0xd78 + _ _ _ _ _ _ _ _ +# 0xd80 + _ _ _ _ _ _ _ _ +# 0xd88 + _ _ _ _ _ _ _ _ +# 0xd90 + _ _ _ _ _ _ _ _ +# 0xd98 + _ _ _ _ _ _ _ _ +# 0xda0 + _ _ _ _ _ _ _ _ +# 0xda8 + _ _ _ _ _ _ _ _ +# 0xdb0 + _ _ _ _ _ _ _ _ +# 0xdb8 + _ _ _ _ _ _ _ _ +# 0xdc0 + _ _ _ _ _ _ _ _ +# 0xdc8 + _ _ _ _ _ _ _ _ +# 0xdd0 + _ _ _ _ _ _ _ _ +# 0xdd8 + _ _ _ _ _ _ _ _ +# 0xde0 + _ _ _ _ _ _ _ _ +# 0xde8 + _ _ _ _ _ _ _ _ +# 0xdf0 + _ _ _ _ _ _ _ _ +# 0xdf8 + _ _ _ _ _ _ _ _ +# 0xe00 + _ _ _ _ _ _ _ _ +# 0xe08 + _ _ _ _ _ _ _ _ +# 0xe10 + _ _ _ _ _ _ _ _ +# 0xe18 + _ _ _ _ _ _ _ _ +# 0xe20 + _ _ _ _ _ _ _ _ +# 0xe28 + _ _ _ _ _ _ _ _ +# 0xe30 + _ _ _ _ _ _ _ _ +# 0xe38 + _ _ _ _ _ _ _ _ +# 0xe40 + _ _ _ _ _ _ _ _ +# 0xe48 + _ _ _ _ _ _ _ _ +# 0xe50 + _ _ _ _ _ _ _ _ +# 0xe58 + _ _ _ _ _ _ _ _ +# 0xe60 + _ _ _ _ _ _ _ _ +# 0xe68 + _ _ _ _ _ _ _ _ +# 0xe70 + _ _ _ _ _ _ _ _ +# 0xe78 + _ _ _ _ _ _ _ _ +# 0xe80 + _ _ _ _ _ _ _ _ +# 0xe88 + _ _ _ _ _ _ _ _ +# 0xe90 + _ _ _ _ _ _ _ _ +# 0xe98 + _ _ _ _ _ _ _ _ +# 0xea0 + _ _ _ _ _ _ _ _ +# 0xea8 + _ _ _ _ _ _ _ _ +# 0xeb0 + _ _ _ _ _ _ _ _ +# 0xeb8 + _ _ _ _ _ _ _ _ +# 0xec0 + _ _ _ _ _ _ _ _ +# 0xec8 + _ _ _ _ _ _ _ _ +# 0xed0 + _ _ _ _ _ _ _ _ +# 0xed8 + _ _ _ _ _ _ _ _ +# 0xee0 + _ _ _ _ _ _ _ _ +# 0xee8 + _ _ _ _ _ _ _ _ +# 0xef0 + _ _ _ _ _ _ _ _ +# 0xef8 + _ _ _ _ _ _ _ _ +# 0xf00 + _ _ _ _ _ _ _ _ +# 0xf08 + _ _ _ _ _ _ _ _ +# 0xf10 + _ _ _ _ _ _ _ _ +# 0xf18 + _ _ _ _ _ _ _ _ +# 0xf20 + _ _ _ _ _ _ _ _ +# 0xf28 + _ _ _ _ _ _ _ _ +# 0xf30 + _ _ _ _ _ _ _ _ +# 0xf38 + _ _ _ _ _ _ _ _ +# 0xf40 + _ _ _ _ _ _ _ _ +# 0xf48 + _ _ _ _ _ _ _ _ +# 0xf50 + _ _ _ _ _ _ _ _ +# 0xf58 + _ _ _ _ _ _ _ _ +# 0xf60 + _ _ _ _ _ _ _ _ +# 0xf68 + _ _ _ _ _ _ _ _ +# 0xf70 + _ _ _ _ _ _ _ _ +# 0xf78 + _ _ _ _ _ _ _ _ +# 0xf80 + _ _ _ _ _ _ _ _ +# 0xf88 + _ _ _ _ _ _ _ _ +# 0xf90 + _ _ _ _ _ _ _ _ +# 0xf98 + _ _ _ _ _ _ _ _ +# 0xfa0 + _ _ _ _ _ _ _ _ +# 0xfa8 + _ _ _ _ _ _ _ _ +# 0xfb0 + _ _ _ _ _ _ _ _ +# 0xfb8 + _ _ _ _ _ _ _ _ +# 0xfc0 + _ _ _ _ _ _ _ _ +# 0xfc8 + _ _ _ _ _ _ _ _ +# 0xfd0 + _ _ _ _ _ _ _ _ +# 0xfd8 + _ _ _ _ _ _ _ _ +# 0xfe0 + _ _ _ _ _ _ _ _ +# 0xfe8 + _ _ _ _ _ _ _ _ +# 0xff0 + _ _ _ _ _ _ _ _ +# 0xff8 + _ _ _ _ _ _ _ _ +]; + + + + +define context CONTEXT + reserved=(0,3) + MXL=(4,5) # MXL - Machine XLEN {1: 32, 2: 64, 3: 128} ; @@ -644,12 +1154,19 @@ define token instr (32) r0711=(7,11) fr0711=(7,11) v0711=(7,11) + op0808=(8,8) + op0809=(8,9) op0811=(8,11) + op0911=(9,11) + op1011=(10,11) + op1213=(12,13) op1214=(12,14) funct3=(12,14) op1219=(12,19) op1231=(12,31) sop1231=(12,31) signed + op1414=(14,14) + op1516=(15,16) op1519=(15,19) sop1519=(15,19) signed subf5=(15,19) @@ -658,6 +1175,7 @@ define token instr (32) v1519=(15,19) op1527=(15,27) op1531=(15,31) + op1719=(17,19) op2020=(20,20) op2022=(20,22) succ=(20,23) @@ -710,10 +1228,13 @@ define token instr (32) op2031=(20,31) sop2031=(20,31) signed op2121=(21,21) + op2122=(21,22) op2130=(21,30) op2222=(22,22) + op2230=(22,30) op2323=(23,23) op2324=(23,24) + op2330=(23,30) op2424=(24,24) op2427=(24,27) pred=(24,27) @@ -739,6 +1260,7 @@ define token instr (32) op2829=(28,29) fm=(28,31) op2931=(29,31) + op3030=(30,30) op3031=(30,31) op3131=(31,31) sop3131=(31,31) signed @@ -774,6 +1296,7 @@ define token cinstr (16) cop0710=(7,10) cop0711=(7,11) cr0711=(7,11) + cd0711NoSp=(7,11) cd0711=(7,11) cfr0711=(7,11) cop0712=(7,12) @@ -792,582 +1315,3 @@ define token cinstr (16) ; -attach variables [ r0711 r1519 r2024 r2731 ] - [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 - a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; - -attach variables [ cr0206 cr0711 cd0711 ] - [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 - a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; - -attach variables [ cr0204s cr0709s cd0709s ] - [ s0 s1 a0 a1 a2 a3 a4 a5 ]; - - -attach variables [ fr0711 fr1519 fr2024 fr2731 ] - [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 - fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; - -attach variables [ cfr0206 cfr0711 ] - [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 - fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; - -attach variables [ cfr0204s cfr0709s ] - [ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ]; - - -attach variables [ v0711 v1519 v2024 ] - [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 - v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ]; - - -attach variables [ csr_0 ] - [ ustatus fflags frm fcsr uie utvec csr006 csr007 - vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr - csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017 - csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f - csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027 - csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f - csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037 - csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f - uscratch uepc ucause utval uip csr045 csr046 csr047 - csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f - csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057 - csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f - csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067 - csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f - csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077 - csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f - csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087 - csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f - csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097 - csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f - csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7 - csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af - csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7 - csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf - csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7 - csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf - csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7 - csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df - csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7 - csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef - csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7 - csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff ]; -attach variables [ csr_1 ] - [ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107 - csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f - csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117 - csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f - csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 - csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f - csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137 - csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f - sscratch sepc scause stval sip csr145 csr146 csr147 - csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f - csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157 - csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f - csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 - csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f - csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177 - csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f - satp csr181 csr182 csr183 csr184 csr185 csr186 csr187 - csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f - csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197 - csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f - csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7 - csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af - csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7 - csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf - csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7 - csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf - csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7 - csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df - csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7 - csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef - csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7 - csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff ]; -attach variables [ csr_2 ] - [ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207 - csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f - csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217 - csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f - csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227 - csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f - csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237 - csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f - vsscratch vsepc vscause vstval vsip csr245 csr246 csr247 - csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f - csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257 - csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f - csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267 - csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f - csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277 - csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f - vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287 - csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f - csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297 - csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f - csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7 - csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af - csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7 - csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf - csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7 - csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf - csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7 - csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df - csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7 - csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef - csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7 - csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff ]; -attach variables [ csr_3 ] - [ mstatus misa medeleg mideleg mie mtvec mcounteren csr307 - csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f - mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317 - csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f - mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 - mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15 - mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 - mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31 - mscratch mepc mcause mtval mip csr345 csr346 csr347 - csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f - csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357 - csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f - csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367 - csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f - csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377 - csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f - mbase mbound mibase mibound mdbase mdbound csr386 csr387 - csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f - csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397 - csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f - pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7 - pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15 - pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 - pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15 - pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23 - pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31 - pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39 - pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47 - pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55 - pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63 - csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7 - csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff ]; -attach variables [ csr_4 ] - [ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407 - csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f - csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417 - csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f - csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427 - csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f - csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437 - csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f - csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447 - csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f - csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457 - csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f - csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467 - csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f - csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477 - csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f - csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487 - csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f - csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497 - csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f - csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7 - csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af - csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7 - csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf - csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7 - csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf - csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7 - csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df - csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7 - csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef - csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7 - csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff ]; -attach variables [ csr_50 ] - [ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507 - csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f - csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517 - csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f - csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527 - csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f - csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537 - csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f - csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547 - csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f - csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557 - csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f - csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567 - csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f - csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577 - csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f ]; -attach variables [ csr_58 ] - [ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587 - csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f - csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597 - csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f - csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7 - scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af - csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7 - csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf ]; -attach variables [ csr_5C ] - [ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7 - csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf - csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7 - csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df - csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7 - csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef - csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7 - csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff ]; -attach variables [ csr_60 ] - [ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie - csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f - csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617 - csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f - csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627 - csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f - csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637 - csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f - csr640 csr641 csr642 htval hip hvip csr646 csr647 - csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f - csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657 - csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f - csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667 - csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f - csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677 - csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f ]; -attach variables [ csr_68 ] - [ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687 - csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f - csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697 - csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f - csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7 - hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af - csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7 - csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf ]; -attach variables [ csr_6C ] - [ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7 - csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf - csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7 - csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df - csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7 - csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef - csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7 - csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff ]; -attach variables [ csr_70 ] - [ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707 - csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f - csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717 - csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f - csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727 - csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f - csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737 - csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f - csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747 - csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f - csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757 - csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f - csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767 - csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f - csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777 - csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f ]; -attach variables [ csr_78 ] - [ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787 - csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f - csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797 - csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f ]; -attach variables [ csr_7A ] - [ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7 - mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af ]; -attach variables [ csr_7B ] - [ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7 - csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf ]; -attach variables [ csr_7C ] - [ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7 - csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf - csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7 - csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df - csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7 - csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef - csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7 - csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff ]; -attach variables [ csr_8 ] - [ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807 - csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f - csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817 - csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f - csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827 - csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f - csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837 - csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f - csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847 - csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f - csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857 - csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f - csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867 - csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f - csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877 - csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f - csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887 - csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f - csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897 - csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f - csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7 - csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af - csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7 - csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf - csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7 - csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf - csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7 - csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df - csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7 - csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef - csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7 - csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff ]; -attach variables [ csr_90 ] - [ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907 - csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f - csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917 - csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f - csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927 - csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f - csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937 - csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f - csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947 - csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f - csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957 - csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f - csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967 - csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f - csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977 - csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f ]; -attach variables [ csr_98 ] - [ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987 - csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f - csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997 - csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f - csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7 - csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af - csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7 - csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf ]; -attach variables [ csr_9C ] - [ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7 - csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf - csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7 - csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df - csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7 - csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef - csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7 - csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff ]; -attach variables [ csr_A0 ] - [ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07 - csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f - csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17 - csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f - csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27 - csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f - csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37 - csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f - csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47 - csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f - csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57 - csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f - csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67 - csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f - csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77 - csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f ]; -attach variables [ csr_A8 ] - [ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87 - csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f - csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97 - csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f - csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7 - csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf - csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7 - csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf ]; -attach variables [ csr_AC ] - [ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7 - csrac8 csrac9 csraca csracb csracc csracd csrace csracf - csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7 - csrad8 csrad9 csrada csradb csradc csradd csrade csradf - csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7 - csrae8 csrae9 csraea csraeb csraec csraed csraee csraef - csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7 - csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff ]; -attach variables [ csr_B0 ] - [ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7 - mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15 - mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23 - mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31 - csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27 - csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f - csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37 - csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f - csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47 - csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f - csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57 - csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f - csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67 - csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f - csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77 - csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f ]; -attach variables [ csr_B8 ] - [ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h - mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h - mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h - mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h - csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7 - csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf - csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7 - csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf ]; -attach variables [ csr_BC ] - [ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7 - csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf - csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7 - csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf - csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7 - csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef - csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7 - csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff ]; -attach variables [ csr_C0 ] - [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7 - hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15 - hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23 - hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31 - vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27 - csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f - csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37 - csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f - csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47 - csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f - csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57 - csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f - csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67 - csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f - csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77 - csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f ]; -attach variables [ csr_C8 ] - [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h - hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h - hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h - hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h - csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7 - csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf - csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7 - csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf ]; -attach variables [ csr_CC ] - [ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7 - csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf - csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7 - csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf - csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7 - csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef - csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7 - csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff ]; -attach variables [ csr_D0 ] - [ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07 - csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f - csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17 - csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f - csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27 - csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f - csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37 - csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f - csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47 - csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f - csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57 - csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f - csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67 - csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f - csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77 - csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f ]; -attach variables [ csr_D8 ] - [ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87 - csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f - csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97 - csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f - csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7 - csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf - csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7 - csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf ]; -attach variables [ csr_DC ] - [ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7 - csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf - csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7 - csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf - csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7 - csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef - csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7 - csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff ]; -attach variables [ csr_E0 ] - [ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07 - csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f - csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17 - csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f - csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27 - csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f - csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37 - csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f - csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47 - csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f - csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57 - csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f - csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67 - csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f - csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77 - csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f ]; -attach variables [ csr_E8 ] - [ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87 - csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f - csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97 - csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f - csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7 - csrea8 csrea9 csreaa csreab csreac csread csreae csreaf - csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7 - csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf ]; -attach variables [ csr_EC ] - [ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7 - csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf - csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7 - csred8 csred9 csreda csredb csredc csredd csrede csredf - csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7 - csree8 csree9 csreea csreeb csreec csreed csreee csreef - csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7 - csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff ]; -attach variables [ csr_F0 ] - [ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07 - csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f - csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17 - csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f - csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27 - csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f - csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37 - csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f - csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47 - csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f - csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57 - csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f - csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67 - csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f - csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77 - csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f ]; -attach variables [ csr_F8 ] - [ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87 - csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f - csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97 - csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f - csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7 - csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf - csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7 - csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf ]; -attach variables [ csr_FC ] - [ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7 - csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf - csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7 - csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf - csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7 - csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef - csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7 - csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff ]; diff --git a/pypcode/processors/RISCV/data/languages/riscv.rvc.sinc b/pypcode/processors/RISCV/data/languages/riscv.rvc.sinc index 480f1b60..367f3d04 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rvc.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rvc.sinc @@ -226,9 +226,9 @@ } # c.lui d,Cu 00006001 0000e003 SIMPLE (0, 0) -:c.lui crd,cbigimm is crd & cbigimm & cop0001=0x1 & cop1315=0x3 +:c.lui cd0711NoSp,cbigimm is cd0711NoSp & cbigimm & cop0001=0x1 & cop1315=0x3 { - crd = cbigimm; + cd0711NoSp = cbigimm; } # c.lw Ct,Ck(Cs) 00004000 0000e003 DWORD|DREF (0, 4) diff --git a/pypcode/processors/RISCV/data/languages/riscv.rvv.sinc b/pypcode/processors/RISCV/data/languages/riscv.rvv.sinc index f21ed223..bb37a6c4 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.rvv.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.rvv.sinc @@ -41,19 +41,19 @@ # vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vaadd.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] + vs1[i], 1) -:vaadd.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vaadd.vv vd, vs2, vs1^ vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vaadd.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] + x[rs1], 1) -:vaadd.vx vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vaadd.vx vd, vs2, rs1^ vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vaaddu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] + vs1[i], 1) -:vaaddu.vv vd, vs2, vs1, vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vaaddu.vv vd, vs2, vs1^ vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vaaddu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] + x[rs1], 1) -:vaaddu.vx vd, vs2, rs1, vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vaaddu.vx vd, vs2, rs1^ vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 # vadc.vim vd, vs2, simm5, v0 # Vector-immediate @@ -69,331 +69,331 @@ # vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vadd.vi vd, vs2, simm5, vm # vector-immediate -:vadd.vi vd, vs2, simm5, vm is op2631=0x0 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vadd.vi vd, vs2, simm5^ vm is op2631=0x0 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vadd.vv vd, vs2, vs1, vm # Vector-vector -:vadd.vv vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vadd.vv vd, vs2, vs1^ vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vadd.vx vd, vs2, rs1, vm # vector-scalar -:vadd.vx vd, vs2, rs1, vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vadd.vx vd, vs2, rs1^ vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoaddei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoaddei16.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamoaddei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamoaddei16.v 31..27=0x00 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoaddei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoaddei16.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl +:vamoaddei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl # vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoaddei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoaddei32.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamoaddei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamoaddei32.v 31..27=0x00 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoaddei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoaddei32.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & vd & op0006=0x2f unimpl +:vamoaddei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & vd & op0006=0x2f unimpl # vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoaddei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoaddei64.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamoaddei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamoaddei64.v 31..27=0x00 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoaddei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoaddei64.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & vd & op0006=0x2f unimpl +:vamoaddei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & vd & op0006=0x2f unimpl # vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoaddei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoaddei8.v vd, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamoaddei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamoaddei8.v 31..27=0x00 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoaddei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoaddei8.v zero, (rs1), vs2, vs3, vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl +:vamoaddei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x0 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl # vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoandei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoandei16.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamoandei16.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamoandei16.v 31..27=0x0c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoandei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoandei16.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl +:vamoandei16.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & vd & op0006=0x2f unimpl # vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoandei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoandei32.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamoandei32.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamoandei32.v 31..27=0x0c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoandei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoandei32.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamoandei32.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoandei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoandei64.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamoandei64.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamoandei64.v 31..27=0x0c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoandei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoandei64.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamoandei64.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoandei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoandei8.v vd, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamoandei8.v vd, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamoandei8.v 31..27=0x0c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoandei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoandei8.v zero, (rs1), vs2, vs3, vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl +:vamoandei8.v zero, (rs1), vs2, vs3^ vm is op2731=0xc & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl # vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamomaxei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxei16.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamomaxei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamomaxei16.v 31..27=0x14 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamomaxei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxei16.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl +:vamomaxei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl # vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamomaxei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxei32.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamomaxei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamomaxei32.v 31..27=0x14 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamomaxei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxei32.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamomaxei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamomaxei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxei64.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamomaxei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamomaxei64.v 31..27=0x14 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamomaxei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxei64.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamomaxei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamomaxei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxei8.v vd, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamomaxei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamomaxei8.v 31..27=0x14 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamomaxei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxei8.v zero, (rs1), vs2, vs3, vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl +:vamomaxei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x14 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl # vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamomaxuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxuei16.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamomaxuei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamomaxuei16.v 31..27=0x1c wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamomaxuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxuei16.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl +:vamomaxuei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl # vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamomaxuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxuei32.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamomaxuei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamomaxuei32.v 31..27=0x1c wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamomaxuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxuei32.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamomaxuei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamomaxuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxuei64.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamomaxuei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamomaxuei64.v 31..27=0x1c wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamomaxuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxuei64.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamomaxuei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamomaxuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamomaxuei8.v vd, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamomaxuei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamomaxuei8.v 31..27=0x1c wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamomaxuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamomaxuei8.v zero, (rs1), vs2, vs3, vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl +:vamomaxuei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x1c & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl # vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamominei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominei16.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamominei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamominei16.v 31..27=0x10 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamominei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominei16.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl +:vamominei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl # vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamominei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominei32.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamominei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamominei32.v 31..27=0x10 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamominei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominei32.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamominei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamominei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominei64.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamominei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamominei64.v 31..27=0x10 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamominei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominei64.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamominei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamominei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominei8.v vd, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamominei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamominei8.v 31..27=0x10 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamominei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominei8.v zero, (rs1), vs2, vs3, vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl +:vamominei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x10 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl # vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamominuei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominuei16.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamominuei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamominuei16.v 31..27=0x18 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamominuei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominuei16.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl +:vamominuei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl # vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamominuei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominuei32.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamominuei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamominuei32.v 31..27=0x18 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamominuei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominuei32.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamominuei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamominuei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominuei64.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamominuei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamominuei64.v 31..27=0x18 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamominuei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominuei64.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamominuei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamominuei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamominuei8.v vd, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamominuei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamominuei8.v 31..27=0x18 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamominuei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamominuei8.v zero, (rs1), vs2, vs3, vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl +:vamominuei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x18 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl # vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoorei16.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamoorei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamoorei16.v 31..27=0x08 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoorei16.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl +:vamoorei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl # vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoorei32.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamoorei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamoorei32.v 31..27=0x08 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoorei32.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamoorei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoorei64.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamoorei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamoorei64.v 31..27=0x08 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoorei64.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamoorei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoorei8.v vd, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamoorei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamoorei8.v 31..27=0x08 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoorei8.v zero, (rs1), vs2, vs3, vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl +:vamoorei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x8 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl # vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoswapei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoswapei16.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamoswapei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamoswapei16.v 31..27=0x01 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoswapei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoswapei16.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl +:vamoswapei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl # vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoswapei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoswapei32.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamoswapei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamoswapei32.v 31..27=0x01 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoswapei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoswapei32.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamoswapei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoswapei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoswapei64.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamoswapei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamoswapei64.v 31..27=0x01 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoswapei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoswapei64.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamoswapei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoswapei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoswapei8.v vd, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamoswapei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamoswapei8.v 31..27=0x01 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoswapei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoswapei8.v zero, (rs1), vs2, vs3, vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl +:vamoswapei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x1 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & op0006=0x2f unimpl # vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoxorei16.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoxorei16.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl +:vamoxorei16.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & vd & op0006=0x2f unimpl # vamoxorei16.v 31..27=0x04 wd vm vs2 rs1 14..12=0x5 vd 6..0=0x2f # vamoxorei16.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoxorei16.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl +:vamoxorei16.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x5 & zero & vs3 & op0006=0x2f unimpl # vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoxorei32.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoxorei32.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl +:vamoxorei32.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & vd & op0006=0x2f unimpl # vamoxorei32.v 31..27=0x04 wd vm vs2 rs1 14..12=0x6 vd 6..0=0x2f # vamoxorei32.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoxorei32.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl +:vamoxorei32.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x6 & zero & vs3 & op0006=0x2f unimpl # vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoxorei64.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoxorei64.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl +:vamoxorei64.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & vd & op0006=0x2f unimpl # vamoxorei64.v 31..27=0x04 wd vm vs2 rs1 14..12=0x7 vd 6..0=0x2f # vamoxorei64.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoxorei64.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl +:vamoxorei64.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x7 & zero & vs3 & op0006=0x2f unimpl # vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoxorei8.v vd, (rs1), vs2, vs3, vm # Write original value to register, wd=1 -:vamoxorei8.v vd, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl +:vamoxorei8.v vd, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & vd & op0006=0x2f unimpl # vamoxorei8.v 31..27=0x04 wd vm vs2 rs1 14..12=0x0 vd 6..0=0x2f # vamoxorei8.v zero, (rs1), vs2, vs3, vm # Do not write original value to register, wd=0 -:vamoxorei8.v zero, (rs1), vs2, vs3, vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl +:vamoxorei8.v zero, (rs1), vs2, vs3^ vm is op2731=0x4 & wd=0x0 & vm & vs2 & rs1 & op1214=0x0 & zero & vs3 & vd & op0006=0x2f unimpl # vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vand.vi vd, vs2, simm5, vm # vector-immediate -:vand.vi vd, vs2, simm5, vm is op2631=0x9 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vand.vi vd, vs2, simm5^ vm is op2631=0x9 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vand.vv vd, vs2, vs1, vm # Vector-vector -:vand.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vand.vv vd, vs2, vs1^ vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vand.vx vd, vs2, rs1, vm # vector-scalar -:vand.vx vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vand.vx vd, vs2, rs1^ vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vasub.vv vd, vs2, vs1, vm # roundoff_signed(vs2[i] - vs1[i], 1) -:vasub.vv vd, vs2, vs1, vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vasub.vv vd, vs2, vs1^ vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vasub.vx vd, vs2, rs1, vm # roundoff_signed(vs2[i] - x[rs1], 1) -:vasub.vx vd, vs2, rs1, vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vasub.vx vd, vs2, rs1^ vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vasubu.vv vd, vs2, vs1, vm # roundoff_unsigned(vs2[i] - vs1[i], 1) -:vasubu.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vasubu.vv vd, vs2, vs1^ vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vasubu.vx vd, vs2, rs1, vm # roundoff_unsigned(vs2[i] - x[rs1], 1) -:vasubu.vx vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vasubu.vx vd, vs2, rs1^ vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 # vcompress.vm vd, vs2, vs1 # Compress into vd elements of vs2 where vs1 is enabled @@ -401,103 +401,103 @@ # vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vdiv.vv vd, vs2, vs1, vm # Vector-vector -:vdiv.vv vd, vs2, vs1, vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vdiv.vv vd, vs2, vs1^ vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vdiv.vx vd, vs2, rs1, vm # vector-scalar -:vdiv.vx vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vdiv.vx vd, vs2, rs1^ vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vdivu.vv vd, vs2, vs1, vm # Vector-vector -:vdivu.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vdivu.vv vd, vs2, vs1^ vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vdivu.vx vd, vs2, rs1, vm # vector-scalar -:vdivu.vx vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vdivu.vx vd, vs2, rs1^ vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vdot.vv vd, vs2, vs1, vm # Vector-vector -:vdot.vv vd, vs2, vs1, vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vdot.vv vd, vs2, vs1^ vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vdotu.vv 31..26=0x38 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vdotu.vv vd, vs2, vs1, vm # Vector-vector -:vdotu.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vdotu.vv vd, vs2, vs1^ vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfadd.vf vd, vs2, rs1, vm # vector-scalar -:vfadd.vf vd, vs2, rs1, vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfadd.vf vd, vs2, rs1^ vm is op2631=0x0 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfadd.vv vd, vs2, vs1, vm # Vector-vector -:vfadd.vv vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfadd.vv vd, vs2, vs1^ vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 # vfclass.v vd, vs2, vm # Vector-vector -:vfclass.v vd, vs2, vm is op2631=0x13 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfclass.v vd, vs2^ vm is op2631=0x13 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl # vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 # vfcvt.f.x.v vd, vs2, vm # Convert signed integer to float. -:vfcvt.f.x.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfcvt.f.x.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x1 & vd & op0006=0x57 unimpl # vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 # vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. -:vfcvt.f.xu.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfcvt.f.xu.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x1 & vd & op0006=0x57 unimpl # vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 # vfcvt.rtz.x.f.v vd, vs2, vm # Convert float to signed integer, truncating. -:vfcvt.rtz.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfcvt.rtz.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x1 & vd & op0006=0x57 unimpl # vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 # vfcvt.rtz.xu.f.v vd, vs2, vm # Convert float to unsigned integer, truncating. -:vfcvt.rtz.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfcvt.rtz.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x1 & vd & op0006=0x57 unimpl # vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 # vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. -:vfcvt.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfcvt.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 # vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. -:vfcvt.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfcvt.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl # vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfdiv.vf vd, vs2, rs1, vm # vector-scalar -:vfdiv.vf vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfdiv.vf vd, vs2, rs1^ vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfdiv.vv vd, vs2, vs1, vm # Vector-vector -:vfdiv.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfdiv.vv vd, vs2, vs1^ vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfdot.vv 31..26=0x39 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfdot.vv vd, vs2, vs1, vm # Vector-vector -:vfdot.vv vd, vs2, vs1, vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfdot.vv vd, vs2, vs1^ vm is op2631=0x39 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 # vfirst.m rd, vs2, vm -:vfirst.m rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x11 & op1214=0x2 & rd & op0006=0x57 unimpl +:vfirst.m rd, vs2^ vm is op2631=0x10 & vm & vs2 & op1519=0x11 & op1214=0x2 & rd & op0006=0x57 unimpl # vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] -:vfmacc.vf vd, rs1, vs2, vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfmacc.vf vd, rs1, vs2^ vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] -:vfmacc.vv vd, vs1, vs2, vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfmacc.vv vd, vs1, vs2^ vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmadd.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) + vs2[i] -:vfmadd.vf vd, rs1, vs2, vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfmadd.vf vd, rs1, vs2^ vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfmadd.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) + vs2[i] -:vfmadd.vv vd, vs1, vs2, vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfmadd.vv vd, vs1, vs2^ vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmax.vf vd, vs2, rs1, vm # vector-scalar -:vfmax.vf vd, vs2, rs1, vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfmax.vf vd, vs2, rs1^ vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfmax.vv vd, vs2, vs1, vm # Vector-vector -:vfmax.vv vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfmax.vv vd, vs2, vs1^ vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmerge.vfm vd, vs2, rs1, v0 # vd[i] = v0.mask[i] ? f[rs1] : vs2[i] @@ -505,35 +505,35 @@ # vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmin.vf vd, vs2, rs1, vm # vector-scalar -:vfmin.vf vd, vs2, rs1, vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfmin.vf vd, vs2, rs1^ vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfmin.vv vd, vs2, vs1, vm # Vector-vector -:vfmin.vv vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfmin.vv vd, vs2, vs1^ vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] -:vfmsac.vf vd, rs1, vs2, vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfmsac.vf vd, rs1, vs2^ vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] -:vfmsac.vv vd, vs1, vs2, vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfmsac.vv vd, vs1, vs2^ vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmsub.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vd[i]) - vs2[i] -:vfmsub.vf vd, rs1, vs2, vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfmsub.vf vd, rs1, vs2^ vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfmsub.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vd[i]) - vs2[i] -:vfmsub.vv vd, vs1, vs2, vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfmsub.vv vd, vs1, vs2^ vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfmul.vf vd, vs2, rs1, vm # vector-scalar -:vfmul.vf vd, vs2, rs1, vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfmul.vf vd, vs2, rs1^ vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfmul.vv vd, vs2, vs1, vm # Vector-vector -:vfmul.vv vd, vs2, vs1, vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfmul.vv vd, vs2, vs1^ vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 # vfmv.f.s rd, vs2 # f[rd] = vs2[0] (rs1=0) @@ -549,251 +549,251 @@ # vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 # vfncvt.f.f.w vd, vs2, vm # Convert double-width float to single-width float. -:vfncvt.f.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x14 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.f.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x14 & op1214=0x1 & vd & op0006=0x57 unimpl # vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 # vfncvt.f.x.w vd, vs2, vm # Convert double-width signed integer to float. -:vfncvt.f.x.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x13 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.f.x.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x13 & op1214=0x1 & vd & op0006=0x57 unimpl # vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 # vfncvt.f.xu.w vd, vs2, vm # Convert double-width unsigned integer to float. -:vfncvt.f.xu.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x12 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.f.xu.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x12 & op1214=0x1 & vd & op0006=0x57 unimpl # vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 # vfncvt.rod.f.f.w vd, vs2, vm # Convert double-width float to single-width float, -:vfncvt.rod.f.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x15 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.rod.f.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x15 & op1214=0x1 & vd & op0006=0x57 unimpl # vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 # vfncvt.rtz.x.f.w vd, vs2, vm # Convert double-width float to signed integer, truncating. -:vfncvt.rtz.x.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x17 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.rtz.x.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x17 & op1214=0x1 & vd & op0006=0x57 unimpl # vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 # vfncvt.rtz.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer, truncating. -:vfncvt.rtz.xu.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x16 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.rtz.xu.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x16 & op1214=0x1 & vd & op0006=0x57 unimpl # vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 # vfncvt.x.f.w vd, vs2, vm # Convert double-width float to signed integer. -:vfncvt.x.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x11 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.x.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x11 & op1214=0x1 & vd & op0006=0x57 unimpl # vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 # vfncvt.xu.f.w vd, vs2, vm # Convert double-width float to unsigned integer. -:vfncvt.xu.f.w vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfncvt.xu.f.w vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x10 & op1214=0x1 & vd & op0006=0x57 unimpl # vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] -:vfnmacc.vf vd, rs1, vs2, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfnmacc.vf vd, rs1, vs2^ vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] -:vfnmacc.vv vd, vs1, vs2, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfnmacc.vv vd, vs1, vs2^ vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfnmadd.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) - vs2[i] -:vfnmadd.vf vd, rs1, vs2, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfnmadd.vf vd, rs1, vs2^ vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfnmadd.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) - vs2[i] -:vfnmadd.vv vd, vs1, vs2, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfnmadd.vv vd, vs1, vs2^ vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] -:vfnmsac.vf vd, rs1, vs2, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfnmsac.vf vd, rs1, vs2^ vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] -:vfnmsac.vv vd, vs1, vs2, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfnmsac.vv vd, vs1, vs2^ vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfnmsub.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vd[i]) + vs2[i] -:vfnmsub.vf vd, rs1, vs2, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfnmsub.vf vd, rs1, vs2^ vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] -:vfnmsub.vv vd, vs1, vs2, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfnmsub.vv vd, vs1, vs2^ vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfrdiv.vf vd, vs2, rs1, vm # scalar-vector, vd[i] = f[rs1]/vs2[i] -:vfrdiv.vf vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfrdiv.vf vd, vs2, rs1^ vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfredmax.vs vd, vs2, vs1, vm # Maximum value -:vfredmax.vs vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfredmax.vs vd, vs2, vs1^ vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfredmin.vs vd, vs2, vs1, vm # Minimum value -:vfredmin.vs vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfredmin.vs vd, vs2, vs1^ vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfredosum.vs vd, vs2, vs1, vm # Ordered sum -:vfredosum.vs vd, vs2, vs1, vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfredosum.vs vd, vs2, vs1^ vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfredsum.vs vd, vs2, vs1, vm # Unordered sum -:vfredsum.vs vd, vs2, vs1, vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfredsum.vs vd, vs2, vs1^ vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfrsub.vf vd, vs2, rs1, vm # Scalar-vector vd[i] = f[rs1] - vs2[i] -:vfrsub.vf vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfrsub.vf vd, vs2, rs1^ vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfsgnj.vf vd, vs2, rs1, vm # vector-scalar -:vfsgnj.vf vd, vs2, rs1, vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfsgnj.vf vd, vs2, rs1^ vm is op2631=0x8 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfsgnj.vv vd, vs2, vs1, vm # Vector-vector -:vfsgnj.vv vd, vs2, vs1, vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfsgnj.vv vd, vs2, vs1^ vm is op2631=0x8 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfsgnjn.vf vd, vs2, rs1, vm # vector-scalar -:vfsgnjn.vf vd, vs2, rs1, vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfsgnjn.vf vd, vs2, rs1^ vm is op2631=0x9 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfsgnjn.vv vd, vs2, vs1, vm # Vector-vector -:vfsgnjn.vv vd, vs2, vs1, vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfsgnjn.vv vd, vs2, vs1^ vm is op2631=0x9 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfsgnjx.vf vd, vs2, rs1, vm # vector-scalar -:vfsgnjx.vf vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfsgnjx.vf vd, vs2, rs1^ vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfsgnjx.vv vd, vs2, vs1, vm # Vector-vector -:vfsgnjx.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfsgnjx.vv vd, vs2, vs1^ vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] -:vfslide1down.vf vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfslide1down.vf vd, vs2, rs1^ vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] -:vfslide1up.vf vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfslide1up.vf vd, vs2, rs1^ vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 # vfsqrt.v vd, vs2, vm # Vector-vector square root -:vfsqrt.v vd, vs2, vm is op2631=0x13 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfsqrt.v vd, vs2^ vm is op2631=0x13 & vm & vs2 & op1519=0x0 & op1214=0x1 & vd & op0006=0x57 unimpl # vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfsub.vf vd, vs2, rs1, vm # Vector-scalar vd[i] = vs2[i] - f[rs1] -:vfsub.vf vd, vs2, rs1, vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfsub.vf vd, vs2, rs1^ vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfsub.vv vd, vs2, vs1, vm # Vector-vector -:vfsub.vv vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfsub.vv vd, vs2, vs1^ vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwadd.vf vd, vs2, rs1, vm # vector-scalar -:vfwadd.vf vd, vs2, rs1, vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwadd.vf vd, vs2, rs1^ vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwadd.vv vd, vs2, vs1, vm # vector-vector -:vfwadd.vv vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwadd.vv vd, vs2, vs1^ vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwadd.wf vd, vs2, rs1, vm # vector-scalar -:vfwadd.wf vd, vs2, rs1, vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwadd.wf vd, vs2, rs1^ vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwadd.wv vd, vs2, vs1, vm # vector-vector -:vfwadd.wv vd, vs2, vs1, vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwadd.wv vd, vs2, vs1^ vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 # vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width float. -:vfwcvt.f.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xc & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwcvt.f.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xc & op1214=0x1 & vd & op0006=0x57 unimpl # vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 # vfwcvt.f.x.v vd, vs2, vm # Convert signed integer to double-width float. -:vfwcvt.f.x.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xb & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwcvt.f.x.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xb & op1214=0x1 & vd & op0006=0x57 unimpl # vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 # vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float. -:vfwcvt.f.xu.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xa & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwcvt.f.xu.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xa & op1214=0x1 & vd & op0006=0x57 unimpl # vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 # vfwcvt.rtz.x.f.v vd, vs2, vm # Convert float to double-width signed integer, truncating. -:vfwcvt.rtz.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xf & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwcvt.rtz.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xf & op1214=0x1 & vd & op0006=0x57 unimpl # vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 # vfwcvt.rtz.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer, truncating. -:vfwcvt.rtz.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0xe & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwcvt.rtz.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0xe & op1214=0x1 & vd & op0006=0x57 unimpl # vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 # vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. -:vfwcvt.x.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x9 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwcvt.x.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x9 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 # vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer. -:vfwcvt.xu.f.v vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x8 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwcvt.xu.f.v vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x8 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] -:vfwmacc.vf vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwmacc.vf vd, rs1, vs2^ vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] -:vfwmacc.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwmacc.vv vd, vs1, vs2^ vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] -:vfwmsac.vf vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwmsac.vf vd, rs1, vs2^ vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] -:vfwmsac.vv vd, vs1, vs2, vm is op2631=0x3e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwmsac.vv vd, vs1, vs2^ vm is op2631=0x3e & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwmul.vf vd, vs2, rs1, vm # vector-scalar -:vfwmul.vf vd, vs2, rs1, vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwmul.vf vd, vs2, rs1^ vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwmul.vv vd, vs2, vs1, vm # vector-vector -:vfwmul.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwmul.vv vd, vs2, vs1^ vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] -:vfwnmacc.vf vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwnmacc.vf vd, rs1, vs2^ vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] -:vfwnmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwnmacc.vv vd, vs1, vs2^ vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] -:vfwnmsac.vf vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwnmsac.vf vd, rs1, vs2^ vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] -:vfwnmsac.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwnmsac.vv vd, vs1, vs2^ vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwredosum.vs vd, vs2, vs1, vm # Ordered sum -:vfwredosum.vs vd, vs2, vs1, vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwredosum.vs vd, vs2, vs1^ vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwredsum.vs vd, vs2, vs1, vm # Unordered sum -:vfwredsum.vs vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwredsum.vs vd, vs2, vs1^ vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwsub.vf vd, vs2, rs1, vm # vector-scalar -:vfwsub.vf vd, vs2, rs1, vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwsub.vf vd, vs2, rs1^ vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwsub.vv vd, vs2, vs1, vm # vector-vector -:vfwsub.vv vd, vs2, vs1, vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwsub.vv vd, vs2, vs1^ vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vfwsub.wf vd, vs2, rs1, vm # vector-scalar -:vfwsub.wf vd, vs2, rs1, vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vfwsub.wf vd, vs2, rs1^ vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vfwsub.wv vd, vs2, vs1, vm # vector-vector -:vfwsub.wv vd, vs2, vs1, vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vfwsub.wv vd, vs2, vs1^ vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 # vid.v vd, vm # Write element ID to destination. -:vid.v vd, vm is op2631=0x14 & vm & op2024=0x0 & op1519=0x11 & op1214=0x2 & vd & op0006=0x57 unimpl +:vid.v vd^ vm is op2631=0x14 & vm & op2024=0x0 & op1519=0x11 & op1214=0x2 & vd & op0006=0x57 unimpl # viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 # viota.m vd, vs2, vm -:viota.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x10 & op1214=0x2 & vd & op0006=0x57 unimpl +:viota.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x10 & op1214=0x2 & vd & op0006=0x57 unimpl # vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 # vl1re16.v vd, (rs1) @@ -861,139 +861,139 @@ # vle1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 # vle1024.v vd, (rs1), vm # 1024-bit unit-stride load -:vle1024.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vle1024.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vle1024ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 # vle1024ff.v vd, (rs1), vm # 1024-bit unit-stride fault-only-first load -:vle1024ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vle1024ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vle128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 # vle128.v vd, (rs1), vm # 128-bit unit-stride load -:vle128.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vle128.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vle128ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 # vle128ff.v vd, (rs1), vm # 128-bit unit-stride fault-only-first load -:vle128ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vle128ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 # vle16.v vd, (rs1), vm # 16-bit unit-stride load -:vle16.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vle16.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 # vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load -:vle16ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vle16ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vle256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 # vle256.v vd, (rs1), vm # 256-bit unit-stride load -:vle256.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vle256.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vle256ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 # vle256ff.v vd, (rs1), vm # 256-bit unit-stride fault-only-first load -:vle256ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vle256ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 # vle32.v vd, (rs1), vm # 32-bit unit-stride load -:vle32.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vle32.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 # vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load -:vle32ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vle32ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vle512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 # vle512.v vd, (rs1), vm # 512-bit unit-stride load -:vle512.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vle512.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vle512ff.v nf 28=1 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 # vle512ff.v vd, (rs1), vm # 512-bit unit-stride fault-only-first load -:vle512ff.v vd, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vle512ff.v vd, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 # vle64.v vd, (rs1), vm # 64-bit unit-stride load -:vle64.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vle64.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 # vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load -:vle64ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vle64ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 # vle8.v vd, (rs1), vm # 8-bit unit-stride load -:vle8.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vle8.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 # vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load -:vle8ff.v vd, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vle8ff.v vd, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x10 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vlse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 # vlse1024.v vd, (rs1), rs2, vm # 1024-bit strided load -:vlse1024.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vlse1024.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vlse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 # vlse128.v vd, (rs1), rs2, vm # 128-bit strided load -:vlse128.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vlse128.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 # vlse16.v vd, (rs1), rs2, vm # 16-bit strided load -:vlse16.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vlse16.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vlse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 # vlse256.v vd, (rs1), rs2, vm # 256-bit strided load -:vlse256.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vlse256.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 # vlse32.v vd, (rs1), rs2, vm # 32-bit strided load -:vlse32.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vlse32.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vlse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 # vlse512.v vd, (rs1), rs2, vm # 512-bit strided load -:vlse512.v vd, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vlse512.v vd, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 # vlse64.v vd, (rs1), rs2, vm # 64-bit strided load -:vlse64.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vlse64.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 # vlse8.v vd, (rs1), rs2, vm # 8-bit strided load -:vlse8.v vd, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vlse8.v vd, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vlxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 # vlxei1024.v vd, (rs1), vs2, vm # 1024-bit indexed load of SEW data -:vlxei1024.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vlxei1024.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vlxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 # vlxei128.v vd, (rs1), vs2, vm # 128-bit indexed load of SEW data -:vlxei128.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vlxei128.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vlxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 # vlxei16.v vd, (rs1), vs2, vm # 16-bit indexed load of SEW data -:vlxei16.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vlxei16.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vlxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 # vlxei256.v vd, (rs1), vs2, vm # 256-bit indexed load of SEW data -:vlxei256.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl +:vlxei256.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x7 unimpl # vlxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 # vlxei32.v vd, (rs1), vs2, vm # 32-bit indexed load of SEW data -:vlxei32.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vlxei32.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vlxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 # vlxei512.v vd, (rs1), vs2, vm # 512-bit indexed load of SEW data -:vlxei512.v vd, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl +:vlxei512.v vd, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x7 unimpl # vlxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 # vlxei64.v vd, (rs1), vs2, vm # 64-bit indexed load of SEW data -:vlxei64.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl +:vlxei64.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vd & op0006=0x7 unimpl # vlxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 # vlxei8.v vd, (rs1), vs2, vm # 8-bit indexed load of SEW data -:vlxei8.v vd, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl +:vlxei8.v vd, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vd & op0006=0x7 unimpl # vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] -:vmacc.vv vd, vs1, vs2, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmacc.vv vd, vs1, vs2^ vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] -:vmacc.vx vd, rs1, vs2, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vmacc.vx vd, rs1, vs2^ vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vmadc.vim 31..26=0x11 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmadc.vim vd, vs2, simm5, v0 # Vector-immediate @@ -1009,11 +1009,11 @@ # vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i] -:vmadd.vv vd, vs1, vs2, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmadd.vv vd, vs1, vs2^ vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vmadd.vx vd, rs1, vs2, vm # vd[i] = (x[rs1] * vd[i]) + vs2[i] -:vmadd.vx vd, rs1, vs2, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vmadd.vx vd, rs1, vs2^ vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vmand.mm 31..26=0x19 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmand.mm vd, vs2, vs1 # vd[i] = vs2.mask[i] && vs1.mask[i] @@ -1025,19 +1025,19 @@ # vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmax.vv vd, vs2, vs1, vm # Vector-vector -:vmax.vv vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmax.vv vd, vs2, vs1^ vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmax.vx vd, vs2, rs1, vm # vector-scalar -:vmax.vx vd, vs2, rs1, vm is op2631=0x7 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmax.vx vd, vs2, rs1^ vm is op2631=0x7 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmaxu.vv vd, vs2, vs1, vm # Vector-vector -:vmaxu.vv vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmaxu.vv vd, vs2, vs1^ vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmaxu.vx vd, vs2, rs1, vm # vector-scalar -:vmaxu.vx vd, vs2, rs1, vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmaxu.vx vd, vs2, rs1^ vm is op2631=0x6 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmerge.vim vd, vs2, simm5, v0 # vd[i] = v0.mask[i] ? imm : vs2[i] @@ -1053,59 +1053,59 @@ # vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vmfeq.vf vd, vs2, rs1, vm # vector-scalar -:vmfeq.vf vd, vs2, rs1, vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vmfeq.vf vd, vs2, rs1^ vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vmfeq.vv vd, vs2, vs1, vm # Vector-vector -:vmfeq.vv vd, vs2, vs1, vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vmfeq.vv vd, vs2, vs1^ vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vmfge.vf vd, vs2, rs1, vm # vector-scalar -:vmfge.vf vd, vs2, rs1, vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vmfge.vf vd, vs2, rs1^ vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vmfgt.vf vd, vs2, rs1, vm # vector-scalar -:vmfgt.vf vd, vs2, rs1, vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vmfgt.vf vd, vs2, rs1^ vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vmfle.vf vd, vs2, rs1, vm # vector-scalar -:vmfle.vf vd, vs2, rs1, vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vmfle.vf vd, vs2, rs1^ vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vmfle.vv vd, vs2, vs1, vm # Vector-vector -:vmfle.vv vd, vs2, vs1, vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vmfle.vv vd, vs2, vs1^ vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vmflt.vf vd, vs2, rs1, vm # vector-scalar -:vmflt.vf vd, vs2, rs1, vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vmflt.vf vd, vs2, rs1^ vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vmflt.vv vd, vs2, vs1, vm # Vector-vector -:vmflt.vv vd, vs2, vs1, vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vmflt.vv vd, vs2, vs1^ vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 # vmfne.vf vd, vs2, rs1, vm # vector-scalar -:vmfne.vf vd, vs2, rs1, vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl +:vmfne.vf vd, vs2, rs1^ vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x5 & vd & op0006=0x57 unimpl # vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 # vmfne.vv vd, vs2, vs1, vm # Vector-vector -:vmfne.vv vd, vs2, vs1, vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl +:vmfne.vv vd, vs2, vs1^ vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x1 & vd & op0006=0x57 unimpl # vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmin.vv vd, vs2, vs1, vm # Vector-vector -:vmin.vv vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmin.vv vd, vs2, vs1^ vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmin.vx vd, vs2, rs1, vm # vector-scalar -:vmin.vx vd, vs2, rs1, vm is op2631=0x5 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmin.vx vd, vs2, rs1^ vm is op2631=0x5 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vminu.vv vd, vs2, vs1, vm # Vector-vector -:vminu.vv vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vminu.vv vd, vs2, vs1^ vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vminu.vx vd, vs2, rs1, vm # vector-scalar -:vminu.vx vd, vs2, rs1, vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vminu.vx vd, vs2, rs1^ vm is op2631=0x4 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmnand.mm 31..26=0x1d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmnand.mm vd, vs2, vs1 # vd[i] = !(vs2.mask[i] && vs1.mask[i]) @@ -1133,127 +1133,127 @@ # vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 # vmsbf.m vd, vs2, vm -:vmsbf.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmsbf.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x1 & op1214=0x2 & vd & op0006=0x57 unimpl # vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmseq.vi vd, vs2, simm5, vm # vector-immediate -:vmseq.vi vd, vs2, simm5, vm is op2631=0x18 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vmseq.vi vd, vs2, simm5^ vm is op2631=0x18 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmseq.vv vd, vs2, vs1, vm # Vector-vector -:vmseq.vv vd, vs2, vs1, vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmseq.vv vd, vs2, vs1^ vm is op2631=0x18 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmseq.vx vd, vs2, rs1, vm # vector-scalar -:vmseq.vx vd, vs2, rs1, vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmseq.vx vd, vs2, rs1^ vm is op2631=0x18 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmsgt.vi vd, vs2, simm5, vm # Vector-immediate -:vmsgt.vi vd, vs2, simm5, vm is op2631=0x1f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vmsgt.vi vd, vs2, simm5^ vm is op2631=0x1f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmsgt.vx vd, vs2, rs1, vm # Vector-scalar -:vmsgt.vx vd, vs2, rs1, vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmsgt.vx vd, vs2, rs1^ vm is op2631=0x1f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmsgtu.vi vd, vs2, simm5, vm # Vector-immediate -:vmsgtu.vi vd, vs2, simm5, vm is op2631=0x1e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vmsgtu.vi vd, vs2, simm5^ vm is op2631=0x1e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmsgtu.vx vd, vs2, rs1, vm # Vector-scalar -:vmsgtu.vx vd, vs2, rs1, vm is op2631=0x1e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmsgtu.vx vd, vs2, rs1^ vm is op2631=0x1e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 # vmsif.m vd, vs2, vm -:vmsif.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmsif.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl # vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmsle.vi vd, vs2, simm5, vm # vector-immediate -:vmsle.vi vd, vs2, simm5, vm is op2631=0x1d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vmsle.vi vd, vs2, simm5^ vm is op2631=0x1d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmsle.vv vd, vs2, vs1, vm # Vector-vector -:vmsle.vv vd, vs2, vs1, vm is op2631=0x1d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmsle.vv vd, vs2, vs1^ vm is op2631=0x1d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmsle.vx vd, vs2, rs1, vm # vector-scalar -:vmsle.vx vd, vs2, rs1, vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmsle.vx vd, vs2, rs1^ vm is op2631=0x1d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmsleu.vi vd, vs2, simm5, vm # Vector-immediate -:vmsleu.vi vd, vs2, simm5, vm is op2631=0x1c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vmsleu.vi vd, vs2, simm5^ vm is op2631=0x1c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmsleu.vv vd, vs2, vs1, vm # Vector-vector -:vmsleu.vv vd, vs2, vs1, vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmsleu.vv vd, vs2, vs1^ vm is op2631=0x1c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmsleu.vx vd, vs2, rs1, vm # vector-scalar -:vmsleu.vx vd, vs2, rs1, vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmsleu.vx vd, vs2, rs1^ vm is op2631=0x1c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmslt.vv vd, vs2, vs1, vm # Vector-vector -:vmslt.vv vd, vs2, vs1, vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmslt.vv vd, vs2, vs1^ vm is op2631=0x1b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmslt.vx vd, vs2, rs1, vm # vector-scalar -:vmslt.vx vd, vs2, rs1, vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmslt.vx vd, vs2, rs1^ vm is op2631=0x1b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmsltu.vv vd, vs2, vs1, vm # Vector-vector -:vmsltu.vv vd, vs2, vs1, vm is op2631=0x1a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmsltu.vv vd, vs2, vs1^ vm is op2631=0x1a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmsltu.vx vd, vs2, rs1, vm # Vector-scalar -:vmsltu.vx vd, vs2, rs1, vm is op2631=0x1a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmsltu.vx vd, vs2, rs1^ vm is op2631=0x1a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vmsne.vi vd, vs2, simm5, vm # vector-immediate -:vmsne.vi vd, vs2, simm5, vm is op2631=0x19 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vmsne.vi vd, vs2, simm5^ vm is op2631=0x19 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vmsne.vv vd, vs2, vs1, vm # Vector-vector -:vmsne.vv vd, vs2, vs1, vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vmsne.vv vd, vs2, vs1^ vm is op2631=0x19 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vmsne.vx vd, vs2, rs1, vm # vector-scalar -:vmsne.vx vd, vs2, rs1, vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vmsne.vx vd, vs2, rs1^ vm is op2631=0x19 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 # vmsof.m vd, vs2, vm -:vmsof.m vd, vs2, vm is op2631=0x14 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmsof.m vd, vs2^ vm is op2631=0x14 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl # vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmul.vv vd, vs2, vs1, vm # Vector-vector -:vmul.vv vd, vs2, vs1, vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmul.vv vd, vs2, vs1^ vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vmul.vx vd, vs2, rs1, vm # vector-scalar -:vmul.vx vd, vs2, rs1, vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vmul.vx vd, vs2, rs1^ vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmulh.vv vd, vs2, vs1, vm # Vector-vector -:vmulh.vv vd, vs2, vs1, vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmulh.vv vd, vs2, vs1^ vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vmulh.vx vd, vs2, rs1, vm # vector-scalar -:vmulh.vx vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vmulh.vx vd, vs2, rs1^ vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmulhsu.vv vd, vs2, vs1, vm # Vector-vector -:vmulhsu.vv vd, vs2, vs1, vm is op2631=0x26 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmulhsu.vv vd, vs2, vs1^ vm is op2631=0x26 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vmulhsu.vx vd, vs2, rs1, vm # vector-scalar -:vmulhsu.vx vd, vs2, rs1, vm is op2631=0x26 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vmulhsu.vx vd, vs2, rs1^ vm is op2631=0x26 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vmulhu.vv vd, vs2, vs1, vm # Vector-vector -:vmulhu.vv vd, vs2, vs1, vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vmulhu.vv vd, vs2, vs1^ vm is op2631=0x24 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vmulhu.vx vd, vs2, rs1, vm # vector-scalar -:vmulhu.vx vd, vs2, rs1, vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vmulhu.vx vd, vs2, rs1^ vm is op2631=0x24 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 # vmv.s.x vd, rs1 # vd[0] = x[rs1] (vs2=0) @@ -1303,187 +1303,187 @@ #TODO this is broken # vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vnclip.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_signed(vs2[i], uimm5)) -:vnclip.wi vd, vs2, simm5, vm is op2631=0x2f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vnclip.wi vd, vs2, simm5^ vm is op2631=0x2f & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vnclip.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i], vs1[i])) -:vnclip.wv vd, vs2, vs1, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vnclip.wv vd, vs2, vs1^ vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vnclip.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i], x[rs1])) -:vnclip.wx vd, vs2, rs1, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vnclip.wx vd, vs2, rs1^ vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl #TODO this is broken # vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vnclipu.wi vd, vs2, simm5, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm5)) -:vnclipu.wi vd, vs2, simm5, vm is op2631=0x2e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vnclipu.wi vd, vs2, simm5^ vm is op2631=0x2e & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vnclipu.wv vd, vs2, vs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i])) -:vnclipu.wv vd, vs2, vs1, vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vnclipu.wv vd, vs2, vs1^ vm is op2631=0x2e & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vnclipu.wx vd, vs2, rs1, vm # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1])) -:vnclipu.wx vd, vs2, rs1, vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vnclipu.wx vd, vs2, rs1^ vm is op2631=0x2e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] -:vnmsac.vv vd, vs1, vs2, vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vnmsac.vv vd, vs1, vs2^ vm is op2631=0x2f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] -:vnmsac.vx vd, rs1, vs2, vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vnmsac.vx vd, rs1, vs2^ vm is op2631=0x2f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vnmsub.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vd[i]) + vs2[i] -:vnmsub.vv vd, vs1, vs2, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vnmsub.vv vd, vs1, vs2^ vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i] -:vnmsub.vx vd, rs1, vs2, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vnmsub.vx vd, rs1, vs2^ vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl #TODO this is broken # vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vnsra.wi vd, vs2, simm5, vm # vector-immediate -:vnsra.wi vd, vs2, simm5, vm is op2631=0x2d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vnsra.wi vd, vs2, simm5^ vm is op2631=0x2d & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vnsra.wv vd, vs2, vs1, vm # vector-vector -:vnsra.wv vd, vs2, vs1, vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vnsra.wv vd, vs2, vs1^ vm is op2631=0x2d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vnsra.wx vd, vs2, rs1, vm # vector-scalar -:vnsra.wx vd, vs2, rs1, vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vnsra.wx vd, vs2, rs1^ vm is op2631=0x2d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl #TODO this is broken # vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vnsrl.wi vd, vs2, simm5, vm # vector-immediate -:vnsrl.wi vd, vs2, simm5, vm is op2631=0x2c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vnsrl.wi vd, vs2, simm5^ vm is op2631=0x2c & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vnsrl.wv vd, vs2, vs1, vm # vector-vector -:vnsrl.wv vd, vs2, vs1, vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vnsrl.wv vd, vs2, vs1^ vm is op2631=0x2c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vnsrl.wx vd, vs2, rs1, vm # vector-scalar -:vnsrl.wx vd, vs2, rs1, vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vnsrl.wx vd, vs2, rs1^ vm is op2631=0x2c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vor.vi vd, vs2, simm5, vm # vector-immediate -:vor.vi vd, vs2, simm5, vm is op2631=0xa & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vor.vi vd, vs2, simm5^ vm is op2631=0xa & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vor.vv vd, vs2, vs1, vm # Vector-vector -:vor.vv vd, vs2, vs1, vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vor.vv vd, vs2, vs1^ vm is op2631=0xa & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vor.vx vd, vs2, rs1, vm # vector-scalar -:vor.vx vd, vs2, rs1, vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vor.vx vd, vs2, rs1^ vm is op2631=0xa & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 # vpopc.m rd, vs2, vm # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] ) -:vpopc.m rd, vs2, vm is op2631=0x10 & vm & vs2 & op1519=0x10 & op1214=0x2 & rd & op0006=0x57 unimpl +:vpopc.m rd, vs2^ vm is op2631=0x10 & vm & vs2 & op1519=0x10 & op1214=0x2 & rd & op0006=0x57 unimpl # vqmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vqmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] -:vqmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vqmacc.vv vd, vs1, vs2^ vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vqmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vqmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] -:vqmacc.vx vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vqmacc.vx vd, rs1, vs2^ vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vqmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vqmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] -:vqmaccsu.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vqmaccsu.vv vd, vs1, vs2^ vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vqmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vqmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] -:vqmaccsu.vx vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vqmaccsu.vx vd, rs1, vs2^ vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vqmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vqmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] -:vqmaccu.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vqmaccu.vv vd, vs1, vs2^ vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vqmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vqmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] -:vqmaccu.vx vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vqmaccu.vx vd, rs1, vs2^ vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vqmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vqmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i] -:vqmaccus.vx vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vqmaccus.vx vd, rs1, vs2^ vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredand.vs vd, vs2, vs1, vm # vd[0] = and( vs1[0] , vs2[*] ) -:vredand.vs vd, vs2, vs1, vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredand.vs vd, vs2, vs1^ vm is op2631=0x1 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredmax.vs vd, vs2, vs1, vm # vd[0] = max( vs1[0] , vs2[*] ) -:vredmax.vs vd, vs2, vs1, vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredmax.vs vd, vs2, vs1^ vm is op2631=0x7 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredmaxu.vs vd, vs2, vs1, vm # vd[0] = maxu( vs1[0] , vs2[*] ) -:vredmaxu.vs vd, vs2, vs1, vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredmaxu.vs vd, vs2, vs1^ vm is op2631=0x6 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredmin.vs vd, vs2, vs1, vm # vd[0] = min( vs1[0] , vs2[*] ) -:vredmin.vs vd, vs2, vs1, vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredmin.vs vd, vs2, vs1^ vm is op2631=0x5 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredminu.vs vd, vs2, vs1, vm # vd[0] = minu( vs1[0] , vs2[*] ) -:vredminu.vs vd, vs2, vs1, vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredminu.vs vd, vs2, vs1^ vm is op2631=0x4 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredor.vs vd, vs2, vs1, vm # vd[0] = or( vs1[0] , vs2[*] ) -:vredor.vs vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredor.vs vd, vs2, vs1^ vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs1[0] , vs2[*] ) -:vredsum.vs vd, vs2, vs1, vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredsum.vs vd, vs2, vs1^ vm is op2631=0x0 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vredxor.vs vd, vs2, vs1, vm # vd[0] = xor( vs1[0] , vs2[*] ) -:vredxor.vs vd, vs2, vs1, vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vredxor.vs vd, vs2, vs1^ vm is op2631=0x3 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vrem.vv vd, vs2, vs1, vm # Vector-vector -:vrem.vv vd, vs2, vs1, vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vrem.vv vd, vs2, vs1^ vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vrem.vx vd, vs2, rs1, vm # vector-scalar -:vrem.vx vd, vs2, rs1, vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vrem.vx vd, vs2, rs1^ vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vremu.vv vd, vs2, vs1, vm # Vector-vector -:vremu.vv vd, vs2, vs1, vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vremu.vv vd, vs2, vs1^ vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vremu.vx vd, vs2, rs1, vm # vector-scalar -:vremu.vx vd, vs2, rs1, vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vremu.vx vd, vs2, rs1^ vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl #TODO this is broken # vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vrgather.vi vd, vs2, simm5, vm # vd[i] = (uimm >= VLMAX) ? 0 : vs2[uimm] -:vrgather.vi vd, vs2, simm5, vm is op2631=0xc & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vrgather.vi vd, vs2, simm5^ vm is op2631=0xc & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vrgather.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; -:vrgather.vv vd, vs2, vs1, vm is op2631=0xc & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vrgather.vv vd, vs2, vs1^ vm is op2631=0xc & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[x[rs1]] -:vrgather.vx vd, vs2, rs1, vm is op2631=0xc & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vrgather.vx vd, vs2, rs1^ vm is op2631=0xc & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; -:vrgatherei16.vv vd, vs2, vs1, vm is op2631=0xe & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vrgatherei16.vv vd, vs2, vs1^ vm is op2631=0xe & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vrsub.vi vd, vs2, simm5, vm # vd[i] = imm - vs2[i] -:vrsub.vi vd, vs2, simm5, vm is op2631=0x3 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vrsub.vi vd, vs2, simm5^ vm is op2631=0x3 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vrsub.vx vd, vs2, rs1, vm # vd[i] = rs1 - vs2[i] -:vrsub.vx vd, vs2, rs1, vm is op2631=0x3 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vrsub.vx vd, vs2, rs1^ vm is op2631=0x3 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 # vs1r.v vs3, (rs1) @@ -1503,27 +1503,27 @@ # vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vsadd.vi vd, vs2, simm5, vm # vector-immediate -:vsadd.vi vd, vs2, simm5, vm is op2631=0x21 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vsadd.vi vd, vs2, simm5^ vm is op2631=0x21 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsadd.vv vd, vs2, vs1, vm # Vector-vector -:vsadd.vv vd, vs2, vs1, vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vsadd.vv vd, vs2, vs1^ vm is op2631=0x21 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vsadd.vx vd, vs2, rs1, vm # vector-scalar -:vsadd.vx vd, vs2, rs1, vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vsadd.vx vd, vs2, rs1^ vm is op2631=0x21 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vsaddu.vi vd, vs2, simm5, vm # vector-immediate -:vsaddu.vi vd, vs2, simm5, vm is op2631=0x20 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vsaddu.vi vd, vs2, simm5^ vm is op2631=0x20 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsaddu.vv vd, vs2, vs1, vm # Vector-vector -:vsaddu.vv vd, vs2, vs1, vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vsaddu.vv vd, vs2, vs1^ vm is op2631=0x20 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vsaddu.vx vd, vs2, rs1, vm # vector-scalar -:vsaddu.vx vd, vs2, rs1, vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vsaddu.vx vd, vs2, rs1^ vm is op2631=0x20 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsbc.vvm vd, vs2, vs1, v0 # Vector-vector @@ -1535,35 +1535,35 @@ # vse1024.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 # vse1024.v vs3, (rs1), vm # 1024-bit unit-stride store -:vse1024.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vse1024.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vse128.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 # vse128.v vs3, (rs1), vm # 128-bit unit-stride store -:vse128.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vse128.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl # vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 # vse16.v vs3, (rs1), vm # 16-bit unit-stride store -:vse16.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vse16.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vse256.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 # vse256.v vs3, (rs1), vm # 256-bit unit-stride store -:vse256.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vse256.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 # vse32.v vs3, (rs1), vm # 32-bit unit-stride store -:vse32.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vse32.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vse512.v nf 28=1 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 # vse512.v vs3, (rs1), vm # 512-bit unit-stride store -:vse512.v vs3, (rs1), vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vse512.v vs3, (rs1)^ vm is nf & op2828=0x1 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 # vse64.v vs3, (rs1), vm # 64-bit unit-stride store -:vse64.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vse64.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 # vse8.v vs3, (rs1), vm # 8-bit unit-stride store -:vse8.v vs3, (rs1), vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vse8.v vs3, (rs1)^ vm is nf & op2828=0x0 & op2627=0x0 & vm & op2024=0x0 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl # vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 # vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value @@ -1576,380 +1576,380 @@ # vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 # vsext.vf2 vd, vs2, vm # Sign-extend SEW/2 source to SEW destination -:vsext.vf2 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x2 & vd & op0006=0x57 unimpl +:vsext.vf2 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x7 & op1214=0x2 & vd & op0006=0x57 unimpl # vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57 # vsext.vf4 vd, vs2, vm # Sign-extend SEW/4 source to SEW destination -:vsext.vf4 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x5 & op1214=0x2 & vd & op0006=0x57 unimpl +:vsext.vf4 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x5 & op1214=0x2 & vd & op0006=0x57 unimpl # vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57 # vsext.vf8 vd, vs2, vm # Sign-extend SEW/8 source to SEW destination -:vsext.vf8 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl +:vsext.vf8 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x3 & op1214=0x2 & vd & op0006=0x57 unimpl # vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] -:vslide1down.vx vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vslide1down.vx vd, vs2, rs1^ vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] -:vslide1up.vx vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vslide1up.vx vd, vs2, rs1^ vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl #TODO this is broken # vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vslidedown.vi vd, vs2, simm5[4:0], vm # vd[i] = vs2[i+uimm] -:vslidedown.vi vd, vs2, simm5[4:0], vm is op2631=0xf & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vslidedown.vi vd, vs2, simm5[4:0]^ vm is op2631=0xf & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] -:vslidedown.vx vd, vs2, rs1, vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vslidedown.vx vd, vs2, rs1^ vm is op2631=0xf & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl #TODO this is broken # vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vslideup.vi vd, vs2, simm5[4:0], vm # vd[i+uimm] = vs2[i] -:vslideup.vi vd, vs2, simm5[4:0], vm is op2631=0xe & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vslideup.vi vd, vs2, simm5[4:0]^ vm is op2631=0xe & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] -:vslideup.vx vd, vs2, rs1, vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vslideup.vx vd, vs2, rs1^ vm is op2631=0xe & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl #TODO this is broken # vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vsll.vi vd, vs2, simm5, vm # vector-immediate -:vsll.vi vd, vs2, simm5, vm is op2631=0x25 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vsll.vi vd, vs2, simm5^ vm is op2631=0x25 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsll.vv vd, vs2, vs1, vm # Vector-vector -:vsll.vv vd, vs2, vs1, vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vsll.vv vd, vs2, vs1^ vm is op2631=0x25 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vsll.vx vd, vs2, rs1, vm # vector-scalar -:vsll.vx vd, vs2, rs1, vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vsll.vx vd, vs2, rs1^ vm is op2631=0x25 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsmul.vv vd, vs2, vs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*vs1[i], SEW-1)) -:vsmul.vv vd, vs2, vs1, vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vsmul.vv vd, vs2, vs1^ vm is op2631=0x27 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vsmul.vx vd, vs2, rs1, vm # vd[i] = clip(roundoff_signed(vs2[i]*x[rs1], SEW-1)) -:vsmul.vx vd, vs2, rs1, vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vsmul.vx vd, vs2, rs1^ vm is op2631=0x27 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl #OTOD this is broken # vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vsra.vi vd, vs2, simm5, vm # vector-immediate -:vsra.vi vd, vs2, simm5, vm is op2631=0x29 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vsra.vi vd, vs2, simm5^ vm is op2631=0x29 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsra.vv vd, vs2, vs1, vm # Vector-vector -:vsra.vv vd, vs2, vs1, vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vsra.vv vd, vs2, vs1^ vm is op2631=0x29 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vsra.vx vd, vs2, rs1, vm # vector-scalar -:vsra.vx vd, vs2, rs1, vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vsra.vx vd, vs2, rs1^ vm is op2631=0x29 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl #TODO this is broken # vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vsrl.vi vd, vs2, simm5, vm # vector-immediate -:vsrl.vi vd, vs2, simm5, vm is op2631=0x28 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vsrl.vi vd, vs2, simm5^ vm is op2631=0x28 & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsrl.vv vd, vs2, vs1, vm # Vector-vector -:vsrl.vv vd, vs2, vs1, vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vsrl.vv vd, vs2, vs1^ vm is op2631=0x28 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vsrl.vx vd, vs2, rs1, vm # vector-scalar -:vsrl.vx vd, vs2, rs1, vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vsrl.vx vd, vs2, rs1^ vm is op2631=0x28 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vsse1024.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 # vsse1024.v vs3, (rs1), rs2, vm # 1024-bit strided store -:vsse1024.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vsse1024.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vsse128.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 # vsse128.v vs3, (rs1), rs2, vm # 128-bit strided store -:vsse128.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vsse128.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl # vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 # vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store -:vsse16.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vsse16.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vsse256.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 # vsse256.v vs3, (rs1), rs2, vm # 256-bit strided store -:vsse256.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vsse256.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 # vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store -:vsse32.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vsse32.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vsse512.v nf 28=1 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 # vsse512.v vs3, (rs1), rs2, vm # 512-bit strided store -:vsse512.v vs3, (rs1), rs2, vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vsse512.v vs3, (rs1), rs2^ vm is nf & op2828=0x1 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 # vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store -:vsse64.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vsse64.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 # vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store -:vsse8.v vs3, (rs1), rs2, vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vsse8.v vs3, (rs1), rs2^ vm is nf & op2828=0x0 & op2627=0x2 & vm & rs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl #TODO this is broken # vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vssra.vi vd, vs2, simm5, vm # vd[i] = roundoff_signed(vs2[i], uimm) -:vssra.vi vd, vs2, simm5, vm is op2631=0x2b & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vssra.vi vd, vs2, simm5^ vm is op2631=0x2b & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vssra.vv vd, vs2, vs1, vm # vd[i] = roundoff_signed(vs2[i],vs1[i]) -:vssra.vv vd, vs2, vs1, vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vssra.vv vd, vs2, vs1^ vm is op2631=0x2b & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vssra.vx vd, vs2, rs1, vm # vd[i] = roundoff_signed(vs2[i], x[rs1]) -:vssra.vx vd, vs2, rs1, vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vssra.vx vd, vs2, rs1^ vm is op2631=0x2b & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl #TODO this is broken # vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vssrl.vi vd, vs2, simm5, vm # vd[i] = roundoff_unsigned(vs2[i], uimm) -:vssrl.vi vd, vs2, simm5, vm is op2631=0x2a & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vssrl.vi vd, vs2, simm5^ vm is op2631=0x2a & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vssrl.vv vd, vs2, vs1, vm # vd[i] = roundoff_unsigned(vs2[i], vs1[i]) -:vssrl.vv vd, vs2, vs1, vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vssrl.vv vd, vs2, vs1^ vm is op2631=0x2a & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vssrl.vx vd, vs2, rs1, vm # vd[i] = roundoff_unsigned(vs2[i], x[rs1]) -:vssrl.vx vd, vs2, rs1, vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vssrl.vx vd, vs2, rs1^ vm is op2631=0x2a & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vssub.vv vd, vs2, vs1, vm # Vector-vector -:vssub.vv vd, vs2, vs1, vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vssub.vv vd, vs2, vs1^ vm is op2631=0x23 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vssub.vx vd, vs2, rs1, vm # vector-scalar -:vssub.vx vd, vs2, rs1, vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vssub.vx vd, vs2, rs1^ vm is op2631=0x23 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vssubu.vv vd, vs2, vs1, vm # Vector-vector -:vssubu.vv vd, vs2, vs1, vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vssubu.vv vd, vs2, vs1^ vm is op2631=0x22 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vssubu.vx vd, vs2, rs1, vm # vector-scalar -:vssubu.vx vd, vs2, rs1, vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vssubu.vx vd, vs2, rs1^ vm is op2631=0x22 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vsub.vv vd, vs2, vs1, vm # Vector-vector -:vsub.vv vd, vs2, vs1, vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vsub.vv vd, vs2, vs1^ vm is op2631=0x2 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vsub.vx vd, vs2, rs1, vm # vector-scalar -:vsub.vx vd, vs2, rs1, vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vsub.vx vd, vs2, rs1^ vm is op2631=0x2 & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vsuxei1024.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 # vsuxei1024.v vs3, (rs1), vs2, vm # unordered 1024-bit indexed store of SEW data -:vsuxei1024.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vsuxei1024.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vsuxei128.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 # vsuxei128.v vs3, (rs1), vs2, vm # unordered 128-bit indexed store of SEW data -:vsuxei128.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vsuxei128.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl # vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 # vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data -:vsuxei16.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vsuxei16.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vsuxei256.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 # vsuxei256.v vs3, (rs1), vs2, vm # unordered 256-bit indexed store of SEW data -:vsuxei256.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vsuxei256.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 # vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data -:vsuxei32.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vsuxei32.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vsuxei512.v nf 28=1 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 # vsuxei512.v vs3, (rs1), vs2, vm # unordered 512-bit indexed store of SEW data -:vsuxei512.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vsuxei512.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 # vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data -:vsuxei64.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vsuxei64.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 # vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data -:vsuxei8.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vsuxei8.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x1 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl # vsxei1024.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 # vsxei1024.v vs3, (rs1), vs2, vm # ordered 1024-bit indexed store of SEW data -:vsxei1024.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vsxei1024.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vsxei128.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 # vsxei128.v vs3, (rs1), vs2, vm # ordered 128-bit indexed store of SEW data -:vsxei128.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vsxei128.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl # vsxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 # vsxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data -:vsxei16.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vsxei16.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vsxei256.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 # vsxei256.v vs3, (rs1), vs2, vm # ordered 256-bit indexed store of SEW data -:vsxei256.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl +:vsxei256.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x5 & vs3 & op0006=0x27 unimpl # vsxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 # vsxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data -:vsxei32.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vsxei32.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vsxei512.v nf 28=1 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 # vsxei512.v vs3, (rs1), vs2, vm # ordered 512-bit indexed store of SEW data -:vsxei512.v vs3, (rs1), vs2, vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl +:vsxei512.v vs3, (rs1), vs2^ vm is nf & op2828=0x1 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x6 & vs3 & op0006=0x27 unimpl # vsxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 # vsxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data -:vsxei64.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl +:vsxei64.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x7 & vs3 & op0006=0x27 unimpl # vsxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 # vsxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data -:vsxei8.v vs3, (rs1), vs2, vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl +:vsxei8.v vs3, (rs1), vs2^ vm is nf & op2828=0x0 & op2627=0x3 & vm & vs2 & rs1 & op1214=0x0 & vs3 & op0006=0x27 unimpl # vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwadd.vv vd, vs2, vs1, vm # vector-vector -:vwadd.vv vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwadd.vv vd, vs2, vs1^ vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwadd.vx vd, vs2, rs1, vm # vector-scalar -:vwadd.vx vd, vs2, rs1, vm is op2631=0x31 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwadd.vx vd, vs2, rs1^ vm is op2631=0x31 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwadd.wv vd, vs2, vs1, vm # vector-vector -:vwadd.wv vd, vs2, vs1, vm is op2631=0x35 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwadd.wv vd, vs2, vs1^ vm is op2631=0x35 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwadd.wx vd, vs2, rs1, vm # vector-scalar -:vwadd.wx vd, vs2, rs1, vm is op2631=0x35 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwadd.wx vd, vs2, rs1^ vm is op2631=0x35 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwaddu.vv vd, vs2, vs1, vm # vector-vector -:vwaddu.vv vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwaddu.vv vd, vs2, vs1^ vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwaddu.vx vd, vs2, rs1, vm # vector-scalar -:vwaddu.vx vd, vs2, rs1, vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwaddu.vx vd, vs2, rs1^ vm is op2631=0x30 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwaddu.wv vd, vs2, vs1, vm # vector-vector -:vwaddu.wv vd, vs2, vs1, vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwaddu.wv vd, vs2, vs1^ vm is op2631=0x34 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwaddu.wx vd, vs2, rs1, vm # vector-scalar -:vwaddu.wx vd, vs2, rs1, vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwaddu.wx vd, vs2, rs1^ vm is op2631=0x34 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] -:vwmacc.vv vd, vs1, vs2, vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwmacc.vv vd, vs1, vs2^ vm is op2631=0x3d & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] -:vwmacc.vx vd, rs1, vs2, vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwmacc.vx vd, rs1, vs2^ vm is op2631=0x3d & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] -:vwmaccsu.vv vd, vs1, vs2, vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwmaccsu.vv vd, vs1, vs2^ vm is op2631=0x3f & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] -:vwmaccsu.vx vd, rs1, vs2, vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwmaccsu.vx vd, rs1, vs2^ vm is op2631=0x3f & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] -:vwmaccu.vv vd, vs1, vs2, vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwmaccu.vv vd, vs1, vs2^ vm is op2631=0x3c & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] -:vwmaccu.vx vd, rs1, vs2, vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwmaccu.vx vd, rs1, vs2^ vm is op2631=0x3c & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i] -:vwmaccus.vx vd, rs1, vs2, vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwmaccus.vx vd, rs1, vs2^ vm is op2631=0x3e & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwmul.vv vd, vs2, vs1, vm# vector-vector -:vwmul.vv vd, vs2, vs1, vm is op2631=0x3b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwmul.vv vd, vs2, vs1^ vm is op2631=0x3b & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwmul.vx vd, vs2, rs1, vm # vector-scalar -:vwmul.vx vd, vs2, rs1, vm is op2631=0x3b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwmul.vx vd, vs2, rs1^ vm is op2631=0x3b & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwmulsu.vv vd, vs2, vs1, vm # vector-vector -:vwmulsu.vv vd, vs2, vs1, vm is op2631=0x3a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwmulsu.vv vd, vs2, vs1^ vm is op2631=0x3a & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwmulsu.vx vd, vs2, rs1, vm # vector-scalar -:vwmulsu.vx vd, vs2, rs1, vm is op2631=0x3a & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwmulsu.vx vd, vs2, rs1^ vm is op2631=0x3a & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwmulu.vv vd, vs2, vs1, vm # vector-vector -:vwmulu.vv vd, vs2, vs1, vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwmulu.vv vd, vs2, vs1^ vm is op2631=0x38 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwmulu.vx vd, vs2, rs1, vm # vector-scalar -:vwmulu.vx vd, vs2, rs1, vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwmulu.vx vd, vs2, rs1^ vm is op2631=0x38 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vwredsum.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(sign-extend(SEW)) -:vwredsum.vs vd, vs2, vs1, vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vwredsum.vs vd, vs2, vs1^ vm is op2631=0x31 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vwredsumu.vs vd, vs2, vs1, vm # 2*SEW = 2*SEW + sum(zero-extend(SEW)) -:vwredsumu.vs vd, vs2, vs1, vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vwredsumu.vs vd, vs2, vs1^ vm is op2631=0x30 & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwsub.vv vd, vs2, vs1, vm # vector-vector -:vwsub.vv vd, vs2, vs1, vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwsub.vv vd, vs2, vs1^ vm is op2631=0x33 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwsub.vx vd, vs2, rs1, vm # vector-scalar -:vwsub.vx vd, vs2, rs1, vm is op2631=0x33 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwsub.vx vd, vs2, rs1^ vm is op2631=0x33 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwsub.wv vd, vs2, vs1, vm # vector-vector -:vwsub.wv vd, vs2, vs1, vm is op2631=0x37 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwsub.wv vd, vs2, vs1^ vm is op2631=0x37 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwsub.wx vd, vs2, rs1, vm # vector-scalar -:vwsub.wx vd, vs2, rs1, vm is op2631=0x37 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwsub.wx vd, vs2, rs1^ vm is op2631=0x37 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwsubu.vv vd, vs2, vs1, vm # vector-vector -:vwsubu.vv vd, vs2, vs1, vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwsubu.vv vd, vs2, vs1^ vm is op2631=0x32 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwsubu.vx vd, vs2, rs1, vm # vector-scalar -:vwsubu.vx vd, vs2, rs1, vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwsubu.vx vd, vs2, rs1^ vm is op2631=0x32 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 # vwsubu.wv vd, vs2, vs1, vm # vector-vector -:vwsubu.wv vd, vs2, vs1, vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl +:vwsubu.wv vd, vs2, vs1^ vm is op2631=0x36 & vm & vs2 & vs1 & op1214=0x2 & vd & op0006=0x57 unimpl # vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 # vwsubu.wx vd, vs2, rs1, vm # vector-scalar -:vwsubu.wx vd, vs2, rs1, vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl +:vwsubu.wx vd, vs2, rs1^ vm is op2631=0x36 & vm & vs2 & rs1 & op1214=0x6 & vd & op0006=0x57 unimpl # vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 # vxor.vi vd, vs2, simm5, vm # vector-immediate -:vxor.vi vd, vs2, simm5, vm is op2631=0xb & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl +:vxor.vi vd, vs2, simm5^ vm is op2631=0xb & vm & vs2 & simm5 & op1214=0x3 & vd & op0006=0x57 unimpl # vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 # vxor.vv vd, vs2, vs1, vm # Vector-vector -:vxor.vv vd, vs2, vs1, vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl +:vxor.vv vd, vs2, vs1^ vm is op2631=0xb & vm & vs2 & vs1 & op1214=0x0 & vd & op0006=0x57 unimpl # vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 # vxor.vx vd, vs2, rs1, vm # vector-scalar -:vxor.vx vd, vs2, rs1, vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl +:vxor.vx vd, vs2, rs1^ vm is op2631=0xb & vm & vs2 & rs1 & op1214=0x4 & vd & op0006=0x57 unimpl # vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 # vzext.vf2 vd, vs2, vm # Zero-extend SEW/2 source to SEW destination -:vzext.vf2 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x2 & vd & op0006=0x57 unimpl +:vzext.vf2 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x6 & op1214=0x2 & vd & op0006=0x57 unimpl # vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57 # vzext.vf4 vd, vs2, vm # Zero-extend SEW/4 source to SEW destination -:vzext.vf4 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x4 & op1214=0x2 & vd & op0006=0x57 unimpl +:vzext.vf4 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x4 & op1214=0x2 & vd & op0006=0x57 unimpl # vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57 # vzext.vf8 vd, vs2, vm # Zero-extend SEW/8 source to SEW destination -:vzext.vf8 vd, vs2, vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl +:vzext.vf8 vd, vs2^ vm is op2631=0x12 & vm & vs2 & op1519=0x2 & op1214=0x2 & vd & op0006=0x57 unimpl diff --git a/pypcode/processors/RISCV/data/languages/riscv.table.sinc b/pypcode/processors/RISCV/data/languages/riscv.table.sinc index 749ac3e8..2cd1ab08 100644 --- a/pypcode/processors/RISCV/data/languages/riscv.table.sinc +++ b/pypcode/processors/RISCV/data/languages/riscv.table.sinc @@ -1,3 +1,587 @@ +attach variables [ r0711 r1519 r2024 r2731 ] + [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; + +attach variables [ cd0711NoSp ] + [ zero ra _ gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; + + +attach variables [ cr0206 cr0711 cd0711 ] + [ zero ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5 + a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6 ]; + +attach variables [ cr0204s cr0709s cd0709s ] + [ s0 s1 a0 a1 a2 a3 a4 a5 ]; + + +attach variables [ fr0711 fr1519 fr2024 fr2731 ] + [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; + +attach variables [ cfr0206 cfr0711 ] + [ ft0 ft1 ft2 ft3 ft4 ft5 ft6 ft7 fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 + fa6 fa7 fs2 fs3 fs4 fs5 fs6 fs7 fs8 fs9 fs10 fs11 ft8 ft9 ft10 ft11 ]; + +attach variables [ cfr0204s cfr0709s ] + [ fs0 fs1 fa0 fa1 fa2 fa3 fa4 fa5 ]; + + +attach variables [ v0711 v1519 v2024 ] + [ v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 + v16 v17 v18 v19 v20 v21 v22 v23 v24 v25 v26 v27 v28 v29 v30 v31 ]; + +#attach variables [ csr_0 ] +# [ ustatus fflags frm fcsr uie utvec csr006 csr007 +# vstart vxsat vxrm csr00b csr00c csr00d csr00e vcsr +# csr010 csr011 csr012 csr013 csr014 csr015 csr016 csr017 +# csr018 csr019 csr01a csr01b csr01c csr01d csr01e csr01f +# csr020 csr021 csr022 csr023 csr024 csr025 csr026 csr027 +# csr028 csr029 csr02a csr02b csr02c csr02d csr02e csr02f +# csr030 csr031 csr032 csr033 csr034 csr035 csr036 csr037 +# csr038 csr039 csr03a csr03b csr03c csr03d csr03e csr03f +# uscratch uepc ucause utval uip csr045 csr046 csr047 +# csr048 csr049 csr04a csr04b csr04c csr04d csr04e csr04f +# csr050 csr051 csr052 csr053 csr054 csr055 csr056 csr057 +# csr058 csr059 csr05a csr05b csr05c csr05d csr05e csr05f +# csr060 csr061 csr062 csr063 csr064 csr065 csr066 csr067 +# csr068 csr069 csr06a csr06b csr06c csr06d csr06e csr06f +# csr070 csr071 csr072 csr073 csr074 csr075 csr076 csr077 +# csr078 csr079 csr07a csr07b csr07c csr07d csr07e csr07f +# csr080 csr081 csr082 csr083 csr084 csr085 csr086 csr087 +# csr088 csr089 csr08a csr08b csr08c csr08d csr08e csr08f +# csr090 csr091 csr092 csr093 csr094 csr095 csr096 csr097 +# csr098 csr099 csr09a csr09b csr09c csr09d csr09e csr09f +# csr0a0 csr0a1 csr0a2 csr0a3 csr0a4 csr0a5 csr0a6 csr0a7 +# csr0a8 csr0a9 csr0aa csr0ab csr0ac csr0ad csr0ae csr0af +# csr0b0 csr0b1 csr0b2 csr0b3 csr0b4 csr0b5 csr0b6 csr0b7 +# csr0b8 csr0b9 csr0ba csr0bb csr0bc csr0bd csr0be csr0bf +# csr0c0 csr0c1 csr0c2 csr0c3 csr0c4 csr0c5 csr0c6 csr0c7 +# csr0c8 csr0c9 csr0ca csr0cb csr0cc csr0cd csr0ce csr0cf +# csr0d0 csr0d1 csr0d2 csr0d3 csr0d4 csr0d5 csr0d6 csr0d7 +# csr0d8 csr0d9 csr0da csr0db csr0dc csr0dd csr0de csr0df +# csr0e0 csr0e1 csr0e2 csr0e3 csr0e4 csr0e5 csr0e6 csr0e7 +# csr0e8 csr0e9 csr0ea csr0eb csr0ec csr0ed csr0ee csr0ef +# csr0f0 csr0f1 csr0f2 csr0f3 csr0f4 csr0f5 csr0f6 csr0f7 +# csr0f8 csr0f9 csr0fa csr0fb csr0fc csr0fd csr0fe csr0ff ]; +#attach variables [ csr_1 ] +# [ sstatus csr101 sedeleg sideleg sie stvec scounteren csr107 +# csr108 csr109 csr10a csr10b csr10c csr10d csr10e csr10f +# csr110 csr111 csr112 csr113 csr114 csr115 csr116 csr117 +# csr118 csr119 csr11a csr11b csr11c csr11d csr11e csr11f +# csr120 csr121 csr122 csr123 csr124 csr125 csr126 csr127 +# csr128 csr129 csr12a csr12b csr12c csr12d csr12e csr12f +# csr130 csr131 csr132 csr133 csr134 csr135 csr136 csr137 +# csr138 csr139 csr13a csr13b csr13c csr13d csr13e csr13f +# sscratch sepc scause stval sip csr145 csr146 csr147 +# csr148 csr149 csr14a csr14b csr14c csr14d csr14e csr14f +# csr150 csr151 csr152 csr153 csr154 csr155 csr156 csr157 +# csr158 csr159 csr15a csr15b csr15c csr15d csr15e csr15f +# csr160 csr161 csr162 csr163 csr164 csr165 csr166 csr167 +# csr168 csr169 csr16a csr16b csr16c csr16d csr16e csr16f +# csr170 csr171 csr172 csr173 csr174 csr175 csr176 csr177 +# csr178 csr179 csr17a csr17b csr17c csr17d csr17e csr17f +# satp csr181 csr182 csr183 csr184 csr185 csr186 csr187 +# csr188 csr189 csr18a csr18b csr18c csr18d csr18e csr18f +# csr190 csr191 csr192 csr193 csr194 csr195 csr196 csr197 +# csr198 csr199 csr19a csr19b csr19c csr19d csr19e csr19f +# csr1a0 csr1a1 csr1a2 csr1a3 csr1a4 csr1a5 csr1a6 csr1a7 +# csr1a8 csr1a9 csr1aa csr1ab csr1ac csr1ad csr1ae csr1af +# csr1b0 csr1b1 csr1b2 csr1b3 csr1b4 csr1b5 csr1b6 csr1b7 +# csr1b8 csr1b9 csr1ba csr1bb csr1bc csr1bd csr1be csr1bf +# csr1c0 csr1c1 csr1c2 csr1c3 csr1c4 csr1c5 csr1c6 csr1c7 +# csr1c8 csr1c9 csr1ca csr1cb csr1cc csr1cd csr1ce csr1cf +# csr1d0 csr1d1 csr1d2 csr1d3 csr1d4 csr1d5 csr1d6 csr1d7 +# csr1d8 csr1d9 csr1da csr1db csr1dc csr1dd csr1de csr1df +# csr1e0 csr1e1 csr1e2 csr1e3 csr1e4 csr1e5 csr1e6 csr1e7 +# csr1e8 csr1e9 csr1ea csr1eb csr1ec csr1ed csr1ee csr1ef +# csr1f0 csr1f1 csr1f2 csr1f3 csr1f4 csr1f5 csr1f6 csr1f7 +# csr1f8 csr1f9 csr1fa csr1fb csr1fc csr1fd csr1fe csr1ff ]; +#attach variables [ csr_2 ] +# [ vsstatus csr201 csr202 csr203 vsie vstvec csr206 csr207 +# csr208 csr209 csr20a csr20b csr20c csr20d csr20e csr20f +# csr210 csr211 csr212 csr213 csr214 csr215 csr216 csr217 +# csr218 csr219 csr21a csr21b csr21c csr21d csr21e csr21f +# csr220 csr221 csr222 csr223 csr224 csr225 csr226 csr227 +# csr228 csr229 csr22a csr22b csr22c csr22d csr22e csr22f +# csr230 csr231 csr232 csr233 csr234 csr235 csr236 csr237 +# csr238 csr239 csr23a csr23b csr23c csr23d csr23e csr23f +# vsscratch vsepc vscause vstval vsip csr245 csr246 csr247 +# csr248 csr249 csr24a csr24b csr24c csr24d csr24e csr24f +# csr250 csr251 csr252 csr253 csr254 csr255 csr256 csr257 +# csr258 csr259 csr25a csr25b csr25c csr25d csr25e csr25f +# csr260 csr261 csr262 csr263 csr264 csr265 csr266 csr267 +# csr268 csr269 csr26a csr26b csr26c csr26d csr26e csr26f +# csr270 csr271 csr272 csr273 csr274 csr275 csr276 csr277 +# csr278 csr279 csr27a csr27b csr27c csr27d csr27e csr27f +# vsatp csr281 csr282 csr283 csr284 csr285 csr286 csr287 +# csr288 csr289 csr28a csr28b csr28c csr28d csr28e csr28f +# csr290 csr291 csr292 csr293 csr294 csr295 csr296 csr297 +# csr298 csr299 csr29a csr29b csr29c csr29d csr29e csr29f +# csr2a0 csr2a1 csr2a2 csr2a3 csr2a4 csr2a5 csr2a6 csr2a7 +# csr2a8 csr2a9 csr2aa csr2ab csr2ac csr2ad csr2ae csr2af +# csr2b0 csr2b1 csr2b2 csr2b3 csr2b4 csr2b5 csr2b6 csr2b7 +# csr2b8 csr2b9 csr2ba csr2bb csr2bc csr2bd csr2be csr2bf +# csr2c0 csr2c1 csr2c2 csr2c3 csr2c4 csr2c5 csr2c6 csr2c7 +# csr2c8 csr2c9 csr2ca csr2cb csr2cc csr2cd csr2ce csr2cf +# csr2d0 csr2d1 csr2d2 csr2d3 csr2d4 csr2d5 csr2d6 csr2d7 +# csr2d8 csr2d9 csr2da csr2db csr2dc csr2dd csr2de csr2df +# csr2e0 csr2e1 csr2e2 csr2e3 csr2e4 csr2e5 csr2e6 csr2e7 +# csr2e8 csr2e9 csr2ea csr2eb csr2ec csr2ed csr2ee csr2ef +# csr2f0 csr2f1 csr2f2 csr2f3 csr2f4 csr2f5 csr2f6 csr2f7 +# csr2f8 csr2f9 csr2fa csr2fb csr2fc csr2fd csr2fe csr2ff ]; +#attach variables [ csr_3 ] +# [ mstatus misa medeleg mideleg mie mtvec mcounteren csr307 +# csr308 csr309 csr30a csr30b csr30c csr30d csr30e csr30f +# mstatush csr311 csr312 csr313 csr314 csr315 csr316 csr317 +# csr318 csr319 csr31a csr31b csr31c csr31d csr31e csr31f +# mcountinhibit csr321 csr322 mhpmevent3 mhpmevent4 mhpmevent5 mhpmevent6 mhpmevent7 +# mhpmevent8 mhpmevent9 mhpmevent10 mhpmevent11 mhpmevent12 mhpmevent13 mhpmevent14 mhpmevent15 +# mhpmevent16 mhpmevent17 mhpmevent18 mhpmevent19 mhpmevent20 mhpmevent21 mhpmevent22 mhpmevent23 +# mhpmevent24 mhpmevent25 mhpmevent26 mhpmevent27 mhpmevent28 mhpmevent29 mhpmevent30 mhpmevent31 +# mscratch mepc mcause mtval mip csr345 csr346 csr347 +# csr348 csr349 mtinst mtval2 csr34c csr34d csr34e csr34f +# csr350 csr351 csr352 csr353 csr354 csr355 csr356 csr357 +# csr358 csr359 csr35a csr35b csr35c csr35d csr35e csr35f +# csr360 csr361 csr362 csr363 csr364 csr365 csr366 csr367 +# csr368 csr369 csr36a csr36b csr36c csr36d csr36e csr36f +# csr370 csr371 csr372 csr373 csr374 csr375 csr376 csr377 +# csr378 csr379 csr37a csr37b csr37c csr37d csr37e csr37f +# mbase mbound mibase mibound mdbase mdbound csr386 csr387 +# csr388 csr389 csr38a csr38b csr38c csr38d csr38e csr38f +# csr390 csr391 csr392 csr393 csr394 csr395 csr396 csr397 +# csr398 csr399 csr39a csr39b csr39c csr39d csr39e csr39f +# pmpcfg0 pmpcfg1 pmpcfg2 pmpcfg3 pmpcfg4 pmpcfg5 pmpcfg6 pmpcfg7 +# pmpcfg8 pmpcfg9 pmpcfg10 pmpcfg11 pmpcfg12 pmpcfg13 pmpcfg14 pmpcfg15 +# pmpaddr0 pmpaddr1 pmpaddr2 pmpaddr3 pmpaddr4 pmpaddr5 pmpaddr6 pmpaddr7 +# pmpaddr8 pmpaddr9 pmpaddr10 pmpaddr11 pmpaddr12 pmpaddr13 pmpaddr14 pmpaddr15 +# pmpaddr16 pmpaddr17 pmpaddr18 pmpaddr19 pmpaddr20 pmpaddr21 pmpaddr22 pmpaddr23 +# pmpaddr24 pmpaddr25 pmpaddr26 pmpaddr27 pmpaddr28 pmpaddr29 pmpaddr30 pmpaddr31 +# pmpaddr32 pmpaddr33 pmpaddr34 pmpaddr35 pmpaddr36 pmpaddr37 pmpaddr38 pmpaddr39 +# pmpaddr40 pmpaddr41 pmpaddr42 pmpaddr43 pmpaddr44 pmpaddr45 pmpaddr46 pmpaddr47 +# pmpaddr48 pmpaddr49 pmpaddr50 pmpaddr51 pmpaddr52 pmpaddr53 pmpaddr54 pmpaddr55 +# pmpaddr56 pmpaddr57 pmpaddr58 pmpaddr59 pmpaddr60 pmpaddr61 pmpaddr62 pmpaddr63 +# csr3f0 csr3f1 csr3f2 csr3f3 csr3f4 csr3f5 csr3f6 csr3f7 +# csr3f8 csr3f9 csr3fa csr3fb csr3fc csr3fd csr3fe csr3ff ]; +#attach variables [ csr_4 ] +# [ csr400 csr401 csr402 csr403 csr404 csr405 csr406 csr407 +# csr408 csr409 csr40a csr40b csr40c csr40d csr40e csr40f +# csr410 csr411 csr412 csr413 csr414 csr415 csr416 csr417 +# csr418 csr419 csr41a csr41b csr41c csr41d csr41e csr41f +# csr420 csr421 csr422 csr423 csr424 csr425 csr426 csr427 +# csr428 csr429 csr42a csr42b csr42c csr42d csr42e csr42f +# csr430 csr431 csr432 csr433 csr434 csr435 csr436 csr437 +# csr438 csr439 csr43a csr43b csr43c csr43d csr43e csr43f +# csr440 csr441 csr442 csr443 csr444 csr445 csr446 csr447 +# csr448 csr449 csr44a csr44b csr44c csr44d csr44e csr44f +# csr450 csr451 csr452 csr453 csr454 csr455 csr456 csr457 +# csr458 csr459 csr45a csr45b csr45c csr45d csr45e csr45f +# csr460 csr461 csr462 csr463 csr464 csr465 csr466 csr467 +# csr468 csr469 csr46a csr46b csr46c csr46d csr46e csr46f +# csr470 csr471 csr472 csr473 csr474 csr475 csr476 csr477 +# csr478 csr479 csr47a csr47b csr47c csr47d csr47e csr47f +# csr480 csr481 csr482 csr483 csr484 csr485 csr486 csr487 +# csr488 csr489 csr48a csr48b csr48c csr48d csr48e csr48f +# csr490 csr491 csr492 csr493 csr494 csr495 csr496 csr497 +# csr498 csr499 csr49a csr49b csr49c csr49d csr49e csr49f +# csr4a0 csr4a1 csr4a2 csr4a3 csr4a4 csr4a5 csr4a6 csr4a7 +# csr4a8 csr4a9 csr4aa csr4ab csr4ac csr4ad csr4ae csr4af +# csr4b0 csr4b1 csr4b2 csr4b3 csr4b4 csr4b5 csr4b6 csr4b7 +# csr4b8 csr4b9 csr4ba csr4bb csr4bc csr4bd csr4be csr4bf +# csr4c0 csr4c1 csr4c2 csr4c3 csr4c4 csr4c5 csr4c6 csr4c7 +# csr4c8 csr4c9 csr4ca csr4cb csr4cc csr4cd csr4ce csr4cf +# csr4d0 csr4d1 csr4d2 csr4d3 csr4d4 csr4d5 csr4d6 csr4d7 +# csr4d8 csr4d9 csr4da csr4db csr4dc csr4dd csr4de csr4df +# csr4e0 csr4e1 csr4e2 csr4e3 csr4e4 csr4e5 csr4e6 csr4e7 +# csr4e8 csr4e9 csr4ea csr4eb csr4ec csr4ed csr4ee csr4ef +# csr4f0 csr4f1 csr4f2 csr4f3 csr4f4 csr4f5 csr4f6 csr4f7 +# csr4f8 csr4f9 csr4fa csr4fb csr4fc csr4fd csr4fe csr4ff ]; +#attach variables [ csr_50 ] +# [ csr500 csr501 csr502 csr503 csr504 csr505 csr506 csr507 +# csr508 csr509 csr50a csr50b csr50c csr50d csr50e csr50f +# csr510 csr511 csr512 csr513 csr514 csr515 csr516 csr517 +# csr518 csr519 csr51a csr51b csr51c csr51d csr51e csr51f +# csr520 csr521 csr522 csr523 csr524 csr525 csr526 csr527 +# csr528 csr529 csr52a csr52b csr52c csr52d csr52e csr52f +# csr530 csr531 csr532 csr533 csr534 csr535 csr536 csr537 +# csr538 csr539 csr53a csr53b csr53c csr53d csr53e csr53f +# csr540 csr541 csr542 csr543 csr544 csr545 csr546 csr547 +# csr548 csr549 csr54a csr54b csr54c csr54d csr54e csr54f +# csr550 csr551 csr552 csr553 csr554 csr555 csr556 csr557 +# csr558 csr559 csr55a csr55b csr55c csr55d csr55e csr55f +# csr560 csr561 csr562 csr563 csr564 csr565 csr566 csr567 +# csr568 csr569 csr56a csr56b csr56c csr56d csr56e csr56f +# csr570 csr571 csr572 csr573 csr574 csr575 csr576 csr577 +# csr578 csr579 csr57a csr57b csr57c csr57d csr57e csr57f ]; +#attach variables [ csr_58 ] +# [ csr580 csr581 csr582 csr583 csr584 csr585 csr586 csr587 +# csr588 csr589 csr58a csr58b csr58c csr58d csr58e csr58f +# csr590 csr591 csr592 csr593 csr594 csr595 csr596 csr597 +# csr598 csr599 csr59a csr59b csr59c csr59d csr59e csr59f +# csr5a0 csr5a1 csr5a2 csr5a3 csr5a4 csr5a5 csr5a6 csr5a7 +# scontext csr5a9 csr5aa csr5ab csr5ac csr5ad csr5ae csr5af +# csr5b0 csr5b1 csr5b2 csr5b3 csr5b4 csr5b5 csr5b6 csr5b7 +# csr5b8 csr5b9 csr5ba csr5bb csr5bc csr5bd csr5be csr5bf ]; +#attach variables [ csr_5C ] +# [ csr5c0 csr5c1 csr5c2 csr5c3 csr5c4 csr5c5 csr5c6 csr5c7 +# csr5c8 csr5c9 csr5ca csr5cb csr5cc csr5cd csr5ce csr5cf +# csr5d0 csr5d1 csr5d2 csr5d3 csr5d4 csr5d5 csr5d6 csr5d7 +# csr5d8 csr5d9 csr5da csr5db csr5dc csr5dd csr5de csr5df +# csr5e0 csr5e1 csr5e2 csr5e3 csr5e4 csr5e5 csr5e6 csr5e7 +# csr5e8 csr5e9 csr5ea csr5eb csr5ec csr5ed csr5ee csr5ef +# csr5f0 csr5f1 csr5f2 csr5f3 csr5f4 csr5f5 csr5f6 csr5f7 +# csr5f8 csr5f9 csr5fa csr5fb csr5fc csr5fd csr5fe csr5ff ]; +#attach variables [ csr_60 ] +# [ hstatus csr601 hedeleg hideleg hie htimedelta hcounteren hgeie +# csr608 csr609 csr60a csr60b csr60c csr60d csr60e csr60f +# csr610 csr611 csr612 csr613 csr614 htimedeltah csr616 csr617 +# csr618 csr619 csr61a csr61b csr61c csr61d csr61e csr61f +# csr620 csr621 csr622 csr623 csr624 csr625 csr626 csr627 +# csr628 csr629 csr62a csr62b csr62c csr62d csr62e csr62f +# csr630 csr631 csr632 csr633 csr634 csr635 csr636 csr637 +# csr638 csr639 csr63a csr63b csr63c csr63d csr63e csr63f +# csr640 csr641 csr642 htval hip hvip csr646 csr647 +# csr648 csr649 htinst csr64b csr64c csr64d csr64e csr64f +# csr650 csr651 csr652 csr653 csr654 csr655 csr656 csr657 +# csr658 csr659 csr65a csr65b csr65c csr65d csr65e csr65f +# csr660 csr661 csr662 csr663 csr664 csr665 csr666 csr667 +# csr668 csr669 csr66a csr66b csr66c csr66d csr66e csr66f +# csr670 csr671 csr672 csr673 csr674 csr675 csr676 csr677 +# csr678 csr679 csr67a csr67b csr67c csr67d csr67e csr67f ]; +#attach variables [ csr_68 ] +# [ hgatp csr681 csr682 csr683 csr684 csr685 csr686 csr687 +# csr688 csr689 csr68a csr68b csr68c csr68d csr68e csr68f +# csr690 csr691 csr692 csr693 csr694 csr695 csr696 csr697 +# csr698 csr699 csr69a csr69b csr69c csr69d csr69e csr69f +# csr6a0 csr6a1 csr6a2 csr6a3 csr6a4 csr6a5 csr6a6 csr6a7 +# hcontext csr6a9 csr6aa csr6ab csr6ac csr6ad csr6ae csr6af +# csr6b0 csr6b1 csr6b2 csr6b3 csr6b4 csr6b5 csr6b6 csr6b7 +# csr6b8 csr6b9 csr6ba csr6bb csr6bc csr6bd csr6be csr6bf ]; +#attach variables [ csr_6C ] +# [ csr6c0 csr6c1 csr6c2 csr6c3 csr6c4 csr6c5 csr6c6 csr6c7 +# csr6c8 csr6c9 csr6ca csr6cb csr6cc csr6cd csr6ce csr6cf +# csr6d0 csr6d1 csr6d2 csr6d3 csr6d4 csr6d5 csr6d6 csr6d7 +# csr6d8 csr6d9 csr6da csr6db csr6dc csr6dd csr6de csr6df +# csr6e0 csr6e1 csr6e2 csr6e3 csr6e4 csr6e5 csr6e6 csr6e7 +# csr6e8 csr6e9 csr6ea csr6eb csr6ec csr6ed csr6ee csr6ef +# csr6f0 csr6f1 csr6f2 csr6f3 csr6f4 csr6f5 csr6f6 csr6f7 +# csr6f8 csr6f9 csr6fa csr6fb csr6fc csr6fd csr6fe csr6ff ]; +#attach variables [ csr_70 ] +# [ csr700 csr701 csr702 csr703 csr704 csr705 csr706 csr707 +# csr708 csr709 csr70a csr70b csr70c csr70d csr70e csr70f +# csr710 csr711 csr712 csr713 csr714 csr715 csr716 csr717 +# csr718 csr719 csr71a csr71b csr71c csr71d csr71e csr71f +# csr720 csr721 csr722 csr723 csr724 csr725 csr726 csr727 +# csr728 csr729 csr72a csr72b csr72c csr72d csr72e csr72f +# csr730 csr731 csr732 csr733 csr734 csr735 csr736 csr737 +# csr738 csr739 csr73a csr73b csr73c csr73d csr73e csr73f +# csr740 csr741 csr742 csr743 csr744 csr745 csr746 csr747 +# csr748 csr749 csr74a csr74b csr74c csr74d csr74e csr74f +# csr750 csr751 csr752 csr753 csr754 csr755 csr756 csr757 +# csr758 csr759 csr75a csr75b csr75c csr75d csr75e csr75f +# csr760 csr761 csr762 csr763 csr764 csr765 csr766 csr767 +# csr768 csr769 csr76a csr76b csr76c csr76d csr76e csr76f +# csr770 csr771 csr772 csr773 csr774 csr775 csr776 csr777 +# csr778 csr779 csr77a csr77b csr77c csr77d csr77e csr77f ]; +#attach variables [ csr_78 ] +# [ csr780 csr781 csr782 csr783 csr784 csr785 csr786 csr787 +# csr788 csr789 csr78a csr78b csr78c csr78d csr78e csr78f +# csr790 csr791 csr792 csr793 csr794 csr795 csr796 csr797 +# csr798 csr799 csr79a csr79b csr79c csr79d csr79e csr79f ]; +#attach variables [ csr_7A ] +# [ tselect tdata1 tdata2 tdata3 csr7a4 csr7a5 csr7a6 csr7a7 +# mcontext csr7a9 csr7aa csr7ab csr7ac csr7ad csr7ae csr7af ]; +#attach variables [ csr_7B ] +# [ dcsr dpc dscratch0 dscratch1 csr7b4 csr7b5 csr7b6 csr7b7 +# csr7b8 csr7b9 csr7ba csr7bb csr7bc csr7bd csr7be csr7bf ]; +#attach variables [ csr_7C ] +# [ csr7c0 csr7c1 csr7c2 csr7c3 csr7c4 csr7c5 csr7c6 csr7c7 +# csr7c8 csr7c9 csr7ca csr7cb csr7cc csr7cd csr7ce csr7cf +# csr7d0 csr7d1 csr7d2 csr7d3 csr7d4 csr7d5 csr7d6 csr7d7 +# csr7d8 csr7d9 csr7da csr7db csr7dc csr7dd csr7de csr7df +# csr7e0 csr7e1 csr7e2 csr7e3 csr7e4 csr7e5 csr7e6 csr7e7 +# csr7e8 csr7e9 csr7ea csr7eb csr7ec csr7ed csr7ee csr7ef +# csr7f0 csr7f1 csr7f2 csr7f3 csr7f4 csr7f5 csr7f6 csr7f7 +# csr7f8 csr7f9 csr7fa csr7fb csr7fc csr7fd csr7fe csr7ff ]; +#attach variables [ csr_8 ] +# [ csr800 csr801 csr802 csr803 csr804 csr805 csr806 csr807 +# csr808 csr809 csr80a csr80b csr80c csr80d csr80e csr80f +# csr810 csr811 csr812 csr813 csr814 csr815 csr816 csr817 +# csr818 csr819 csr81a csr81b csr81c csr81d csr81e csr81f +# csr820 csr821 csr822 csr823 csr824 csr825 csr826 csr827 +# csr828 csr829 csr82a csr82b csr82c csr82d csr82e csr82f +# csr830 csr831 csr832 csr833 csr834 csr835 csr836 csr837 +# csr838 csr839 csr83a csr83b csr83c csr83d csr83e csr83f +# csr840 csr841 csr842 csr843 csr844 csr845 csr846 csr847 +# csr848 csr849 csr84a csr84b csr84c csr84d csr84e csr84f +# csr850 csr851 csr852 csr853 csr854 csr855 csr856 csr857 +# csr858 csr859 csr85a csr85b csr85c csr85d csr85e csr85f +# csr860 csr861 csr862 csr863 csr864 csr865 csr866 csr867 +# csr868 csr869 csr86a csr86b csr86c csr86d csr86e csr86f +# csr870 csr871 csr872 csr873 csr874 csr875 csr876 csr877 +# csr878 csr879 csr87a csr87b csr87c csr87d csr87e csr87f +# csr880 csr881 csr882 csr883 csr884 csr885 csr886 csr887 +# csr888 csr889 csr88a csr88b csr88c csr88d csr88e csr88f +# csr890 csr891 csr892 csr893 csr894 csr895 csr896 csr897 +# csr898 csr899 csr89a csr89b csr89c csr89d csr89e csr89f +# csr8a0 csr8a1 csr8a2 csr8a3 csr8a4 csr8a5 csr8a6 csr8a7 +# csr8a8 csr8a9 csr8aa csr8ab csr8ac csr8ad csr8ae csr8af +# csr8b0 csr8b1 csr8b2 csr8b3 csr8b4 csr8b5 csr8b6 csr8b7 +# csr8b8 csr8b9 csr8ba csr8bb csr8bc csr8bd csr8be csr8bf +# csr8c0 csr8c1 csr8c2 csr8c3 csr8c4 csr8c5 csr8c6 csr8c7 +# csr8c8 csr8c9 csr8ca csr8cb csr8cc csr8cd csr8ce csr8cf +# csr8d0 csr8d1 csr8d2 csr8d3 csr8d4 csr8d5 csr8d6 csr8d7 +# csr8d8 csr8d9 csr8da csr8db csr8dc csr8dd csr8de csr8df +# csr8e0 csr8e1 csr8e2 csr8e3 csr8e4 csr8e5 csr8e6 csr8e7 +# csr8e8 csr8e9 csr8ea csr8eb csr8ec csr8ed csr8ee csr8ef +# csr8f0 csr8f1 csr8f2 csr8f3 csr8f4 csr8f5 csr8f6 csr8f7 +# csr8f8 csr8f9 csr8fa csr8fb csr8fc csr8fd csr8fe csr8ff ]; +#attach variables [ csr_90 ] +# [ csr900 csr901 csr902 csr903 csr904 csr905 csr906 csr907 +# csr908 csr909 csr90a csr90b csr90c csr90d csr90e csr90f +# csr910 csr911 csr912 csr913 csr914 csr915 csr916 csr917 +# csr918 csr919 csr91a csr91b csr91c csr91d csr91e csr91f +# csr920 csr921 csr922 csr923 csr924 csr925 csr926 csr927 +# csr928 csr929 csr92a csr92b csr92c csr92d csr92e csr92f +# csr930 csr931 csr932 csr933 csr934 csr935 csr936 csr937 +# csr938 csr939 csr93a csr93b csr93c csr93d csr93e csr93f +# csr940 csr941 csr942 csr943 csr944 csr945 csr946 csr947 +# csr948 csr949 csr94a csr94b csr94c csr94d csr94e csr94f +# csr950 csr951 csr952 csr953 csr954 csr955 csr956 csr957 +# csr958 csr959 csr95a csr95b csr95c csr95d csr95e csr95f +# csr960 csr961 csr962 csr963 csr964 csr965 csr966 csr967 +# csr968 csr969 csr96a csr96b csr96c csr96d csr96e csr96f +# csr970 csr971 csr972 csr973 csr974 csr975 csr976 csr977 +# csr978 csr979 csr97a csr97b csr97c csr97d csr97e csr97f ]; +#attach variables [ csr_98 ] +# [ csr980 csr981 csr982 csr983 csr984 csr985 csr986 csr987 +# csr988 csr989 csr98a csr98b csr98c csr98d csr98e csr98f +# csr990 csr991 csr992 csr993 csr994 csr995 csr996 csr997 +# csr998 csr999 csr99a csr99b csr99c csr99d csr99e csr99f +# csr9a0 csr9a1 csr9a2 csr9a3 csr9a4 csr9a5 csr9a6 csr9a7 +# csr9a8 csr9a9 csr9aa csr9ab csr9ac csr9ad csr9ae csr9af +# csr9b0 csr9b1 csr9b2 csr9b3 csr9b4 csr9b5 csr9b6 csr9b7 +# csr9b8 csr9b9 csr9ba csr9bb csr9bc csr9bd csr9be csr9bf ]; +#attach variables [ csr_9C ] +# [ csr9c0 csr9c1 csr9c2 csr9c3 csr9c4 csr9c5 csr9c6 csr9c7 +# csr9c8 csr9c9 csr9ca csr9cb csr9cc csr9cd csr9ce csr9cf +# csr9d0 csr9d1 csr9d2 csr9d3 csr9d4 csr9d5 csr9d6 csr9d7 +# csr9d8 csr9d9 csr9da csr9db csr9dc csr9dd csr9de csr9df +# csr9e0 csr9e1 csr9e2 csr9e3 csr9e4 csr9e5 csr9e6 csr9e7 +# csr9e8 csr9e9 csr9ea csr9eb csr9ec csr9ed csr9ee csr9ef +# csr9f0 csr9f1 csr9f2 csr9f3 csr9f4 csr9f5 csr9f6 csr9f7 +# csr9f8 csr9f9 csr9fa csr9fb csr9fc csr9fd csr9fe csr9ff ]; +#attach variables [ csr_A0 ] +# [ csra00 csra01 csra02 csra03 csra04 csra05 csra06 csra07 +# csra08 csra09 csra0a csra0b csra0c csra0d csra0e csra0f +# csra10 csra11 csra12 csra13 csra14 csra15 csra16 csra17 +# csra18 csra19 csra1a csra1b csra1c csra1d csra1e csra1f +# csra20 csra21 csra22 csra23 csra24 csra25 csra26 csra27 +# csra28 csra29 csra2a csra2b csra2c csra2d csra2e csra2f +# csra30 csra31 csra32 csra33 csra34 csra35 csra36 csra37 +# csra38 csra39 csra3a csra3b csra3c csra3d csra3e csra3f +# csra40 csra41 csra42 csra43 csra44 csra45 csra46 csra47 +# csra48 csra49 csra4a csra4b csra4c csra4d csra4e csra4f +# csra50 csra51 csra52 csra53 csra54 csra55 csra56 csra57 +# csra58 csra59 csra5a csra5b csra5c csra5d csra5e csra5f +# csra60 csra61 csra62 csra63 csra64 csra65 csra66 csra67 +# csra68 csra69 csra6a csra6b csra6c csra6d csra6e csra6f +# csra70 csra71 csra72 csra73 csra74 csra75 csra76 csra77 +# csra78 csra79 csra7a csra7b csra7c csra7d csra7e csra7f ]; +#attach variables [ csr_A8 ] +# [ csra80 csra81 csra82 csra83 csra84 csra85 csra86 csra87 +# csra88 csra89 csra8a csra8b csra8c csra8d csra8e csra8f +# csra90 csra91 csra92 csra93 csra94 csra95 csra96 csra97 +# csra98 csra99 csra9a csra9b csra9c csra9d csra9e csra9f +# csraa0 csraa1 csraa2 csraa3 csraa4 csraa5 csraa6 csraa7 +# csraa8 csraa9 csraaa csraab csraac csraad csraae csraaf +# csrab0 csrab1 csrab2 csrab3 csrab4 csrab5 csrab6 csrab7 +# csrab8 csrab9 csraba csrabb csrabc csrabd csrabe csrabf ]; +#attach variables [ csr_AC ] +# [ csrac0 csrac1 csrac2 csrac3 csrac4 csrac5 csrac6 csrac7 +# csrac8 csrac9 csraca csracb csracc csracd csrace csracf +# csrad0 csrad1 csrad2 csrad3 csrad4 csrad5 csrad6 csrad7 +# csrad8 csrad9 csrada csradb csradc csradd csrade csradf +# csrae0 csrae1 csrae2 csrae3 csrae4 csrae5 csrae6 csrae7 +# csrae8 csrae9 csraea csraeb csraec csraed csraee csraef +# csraf0 csraf1 csraf2 csraf3 csraf4 csraf5 csraf6 csraf7 +# csraf8 csraf9 csrafa csrafb csrafc csrafd csrafe csraff ]; +#attach variables [ csr_B0 ] +# [ mcycle csrb01 minstret mhpmcounter3 mhpmcounter4 mhpmcounter5 mhpmcounter6 mhpmcounter7 +# mhpmcounter8 mhpmcounter9 mhpmcounter10 mhpmcounter11 mhpmcounter12 mhpmcounter13 mhpmcounter14 mhpmcounter15 +# mhpmcounter16 mhpmcounter17 mhpmcounter18 mhpmcounter19 mhpmcounter20 mhpmcounter21 mhpmcounter22 mhpmcounter23 +# mhpmcounter24 mhpmcounter25 mhpmcounter26 mhpmcounter27 mhpmcounter28 mhpmcounter29 mhpmcounter30 mhpmcounter31 +# csrb20 csrb21 csrb22 csrb23 csrb24 csrb25 csrb26 csrb27 +# csrb28 csrb29 csrb2a csrb2b csrb2c csrb2d csrb2e csrb2f +# csrb30 csrb31 csrb32 csrb33 csrb34 csrb35 csrb36 csrb37 +# csrb38 csrb39 csrb3a csrb3b csrb3c csrb3d csrb3e csrb3f +# csrb40 csrb41 csrb42 csrb43 csrb44 csrb45 csrb46 csrb47 +# csrb48 csrb49 csrb4a csrb4b csrb4c csrb4d csrb4e csrb4f +# csrb50 csrb51 csrb52 csrb53 csrb54 csrb55 csrb56 csrb57 +# csrb58 csrb59 csrb5a csrb5b csrb5c csrb5d csrb5e csrb5f +# csrb60 csrb61 csrb62 csrb63 csrb64 csrb65 csrb66 csrb67 +# csrb68 csrb69 csrb6a csrb6b csrb6c csrb6d csrb6e csrb6f +# csrb70 csrb71 csrb72 csrb73 csrb74 csrb75 csrb76 csrb77 +# csrb78 csrb79 csrb7a csrb7b csrb7c csrb7d csrb7e csrb7f ]; +#attach variables [ csr_B8 ] +# [ mcycleh csrb81 minstreth mhpmcounter3h mhpmcounter4h mhpmcounter5h mhpmcounter6h mhpmcounter7h +# mhpmcounter8h mhpmcounter9h mhpmcounter10h mhpmcounter11h mhpmcounter12h mhpmcounter13h mhpmcounter14h mhpmcounter15h +# mhpmcounter16h mhpmcounter17h mhpmcounter18h mhpmcounter19h mhpmcounter20h mhpmcounter21h mhpmcounter22h mhpmcounter23h +# mhpmcounter24h mhpmcounter25h mhpmcounter26h mhpmcounter27h mhpmcounter28h mhpmcounter29h mhpmcounter30h mhpmcounter31h +# csrba0 csrba1 csrba2 csrba3 csrba4 csrba5 csrba6 csrba7 +# csrba8 csrba9 csrbaa csrbab csrbac csrbad csrbae csrbaf +# csrbb0 csrbb1 csrbb2 csrbb3 csrbb4 csrbb5 csrbb6 csrbb7 +# csrbb8 csrbb9 csrbba csrbbb csrbbc csrbbd csrbbe csrbbf ]; +#attach variables [ csr_BC ] +# [ csrbc0 csrbc1 csrbc2 csrbc3 csrbc4 csrbc5 csrbc6 csrbc7 +# csrbc8 csrbc9 csrbca csrbcb csrbcc csrbcd csrbce csrbcf +# csrbd0 csrbd1 csrbd2 csrbd3 csrbd4 csrbd5 csrbd6 csrbd7 +# csrbd8 csrbd9 csrbda csrbdb csrbdc csrbdd csrbde csrbdf +# csrbe0 csrbe1 csrbe2 csrbe3 csrbe4 csrbe5 csrbe6 csrbe7 +# csrbe8 csrbe9 csrbea csrbeb csrbec csrbed csrbee csrbef +# csrbf0 csrbf1 csrbf2 csrbf3 csrbf4 csrbf5 csrbf6 csrbf7 +# csrbf8 csrbf9 csrbfa csrbfb csrbfc csrbfd csrbfe csrbff ]; +#attach variables [ csr_C0 ] +# [ cycle time instret hpmcounter3 hpmcounter4 hpmcounter5 hpmcounter6 hpmcounter7 +# hpmcounter8 hpmcounter9 hpmcounter10 hpmcounter11 hpmcounter12 hpmcounter13 hpmcounter14 hpmcounter15 +# hpmcounter16 hpmcounter17 hpmcounter18 hpmcounter19 hpmcounter20 hpmcounter21 hpmcounter22 hpmcounter23 +# hpmcounter24 hpmcounter25 hpmcounter26 hpmcounter27 hpmcounter28 hpmcounter29 hpmcounter30 hpmcounter31 +# vl vtype vlenb csrc23 csrc24 csrc25 csrc26 csrc27 +# csrc28 csrc29 csrc2a csrc2b csrc2c csrc2d csrc2e csrc2f +# csrc30 csrc31 csrc32 csrc33 csrc34 csrc35 csrc36 csrc37 +# csrc38 csrc39 csrc3a csrc3b csrc3c csrc3d csrc3e csrc3f +# csrc40 csrc41 csrc42 csrc43 csrc44 csrc45 csrc46 csrc47 +# csrc48 csrc49 csrc4a csrc4b csrc4c csrc4d csrc4e csrc4f +# csrc50 csrc51 csrc52 csrc53 csrc54 csrc55 csrc56 csrc57 +# csrc58 csrc59 csrc5a csrc5b csrc5c csrc5d csrc5e csrc5f +# csrc60 csrc61 csrc62 csrc63 csrc64 csrc65 csrc66 csrc67 +# csrc68 csrc69 csrc6a csrc6b csrc6c csrc6d csrc6e csrc6f +# csrc70 csrc71 csrc72 csrc73 csrc74 csrc75 csrc76 csrc77 +# csrc78 csrc79 csrc7a csrc7b csrc7c csrc7d csrc7e csrc7f ]; +#attach variables [ csr_C8 ] +# [ cycleh timeh instreth hpmcounter3h hpmcounter4h hpmcounter5h hpmcounter6h hpmcounter7h +# hpmcounter8h hpmcounter9h hpmcounter10h hpmcounter11h hpmcounter12h hpmcounter13h hpmcounter14h hpmcounter15h +# hpmcounter16h hpmcounter17h hpmcounter18h hpmcounter19h hpmcounter20h hpmcounter21h hpmcounter22h hpmcounter23h +# hpmcounter24h hpmcounter25h hpmcounter26h hpmcounter27h hpmcounter28h hpmcounter29h hpmcounter30h hpmcounter31h +# csrca0 csrca1 csrca2 csrca3 csrca4 csrca5 csrca6 csrca7 +# csrca8 csrca9 csrcaa csrcab csrcac csrcad csrcae csrcaf +# csrcb0 csrcb1 csrcb2 csrcb3 csrcb4 csrcb5 csrcb6 csrcb7 +# csrcb8 csrcb9 csrcba csrcbb csrcbc csrcbd csrcbe csrcbf ]; +#attach variables [ csr_CC ] +# [ csrcc0 csrcc1 csrcc2 csrcc3 csrcc4 csrcc5 csrcc6 csrcc7 +# csrcc8 csrcc9 csrcca csrccb csrccc csrccd csrcce csrccf +# csrcd0 csrcd1 csrcd2 csrcd3 csrcd4 csrcd5 csrcd6 csrcd7 +# csrcd8 csrcd9 csrcda csrcdb csrcdc csrcdd csrcde csrcdf +# csrce0 csrce1 csrce2 csrce3 csrce4 csrce5 csrce6 csrce7 +# csrce8 csrce9 csrcea csrceb csrcec csrced csrcee csrcef +# csrcf0 csrcf1 csrcf2 csrcf3 csrcf4 csrcf5 csrcf6 csrcf7 +# csrcf8 csrcf9 csrcfa csrcfb csrcfc csrcfd csrcfe csrcff ]; +#attach variables [ csr_D0 ] +# [ csrd00 csrd01 csrd02 csrd03 csrd04 csrd05 csrd06 csrd07 +# csrd08 csrd09 csrd0a csrd0b csrd0c csrd0d csrd0e csrd0f +# csrd10 csrd11 csrd12 csrd13 csrd14 csrd15 csrd16 csrd17 +# csrd18 csrd19 csrd1a csrd1b csrd1c csrd1d csrd1e csrd1f +# csrd20 csrd21 csrd22 csrd23 csrd24 csrd25 csrd26 csrd27 +# csrd28 csrd29 csrd2a csrd2b csrd2c csrd2d csrd2e csrd2f +# csrd30 csrd31 csrd32 csrd33 csrd34 csrd35 csrd36 csrd37 +# csrd38 csrd39 csrd3a csrd3b csrd3c csrd3d csrd3e csrd3f +# csrd40 csrd41 csrd42 csrd43 csrd44 csrd45 csrd46 csrd47 +# csrd48 csrd49 csrd4a csrd4b csrd4c csrd4d csrd4e csrd4f +# csrd50 csrd51 csrd52 csrd53 csrd54 csrd55 csrd56 csrd57 +# csrd58 csrd59 csrd5a csrd5b csrd5c csrd5d csrd5e csrd5f +# csrd60 csrd61 csrd62 csrd63 csrd64 csrd65 csrd66 csrd67 +# csrd68 csrd69 csrd6a csrd6b csrd6c csrd6d csrd6e csrd6f +# csrd70 csrd71 csrd72 csrd73 csrd74 csrd75 csrd76 csrd77 +# csrd78 csrd79 csrd7a csrd7b csrd7c csrd7d csrd7e csrd7f ]; +#attach variables [ csr_D8 ] +# [ csrd80 csrd81 csrd82 csrd83 csrd84 csrd85 csrd86 csrd87 +# csrd88 csrd89 csrd8a csrd8b csrd8c csrd8d csrd8e csrd8f +# csrd90 csrd91 csrd92 csrd93 csrd94 csrd95 csrd96 csrd97 +# csrd98 csrd99 csrd9a csrd9b csrd9c csrd9d csrd9e csrd9f +# csrda0 csrda1 csrda2 csrda3 csrda4 csrda5 csrda6 csrda7 +# csrda8 csrda9 csrdaa csrdab csrdac csrdad csrdae csrdaf +# csrdb0 csrdb1 csrdb2 csrdb3 csrdb4 csrdb5 csrdb6 csrdb7 +# csrdb8 csrdb9 csrdba csrdbb csrdbc csrdbd csrdbe csrdbf ]; +#attach variables [ csr_DC ] +# [ csrdc0 csrdc1 csrdc2 csrdc3 csrdc4 csrdc5 csrdc6 csrdc7 +# csrdc8 csrdc9 csrdca csrdcb csrdcc csrdcd csrdce csrdcf +# csrdd0 csrdd1 csrdd2 csrdd3 csrdd4 csrdd5 csrdd6 csrdd7 +# csrdd8 csrdd9 csrdda csrddb csrddc csrddd csrdde csrddf +# csrde0 csrde1 csrde2 csrde3 csrde4 csrde5 csrde6 csrde7 +# csrde8 csrde9 csrdea csrdeb csrdec csrded csrdee csrdef +# csrdf0 csrdf1 csrdf2 csrdf3 csrdf4 csrdf5 csrdf6 csrdf7 +# csrdf8 csrdf9 csrdfa csrdfb csrdfc csrdfd csrdfe csrdff ]; +#attach variables [ csr_E0 ] +# [ csre00 csre01 csre02 csre03 csre04 csre05 csre06 csre07 +# csre08 csre09 csre0a csre0b csre0c csre0d csre0e csre0f +# csre10 csre11 hgeip csre13 csre14 csre15 csre16 csre17 +# csre18 csre19 csre1a csre1b csre1c csre1d csre1e csre1f +# csre20 csre21 csre22 csre23 csre24 csre25 csre26 csre27 +# csre28 csre29 csre2a csre2b csre2c csre2d csre2e csre2f +# csre30 csre31 csre32 csre33 csre34 csre35 csre36 csre37 +# csre38 csre39 csre3a csre3b csre3c csre3d csre3e csre3f +# csre40 csre41 csre42 csre43 csre44 csre45 csre46 csre47 +# csre48 csre49 csre4a csre4b csre4c csre4d csre4e csre4f +# csre50 csre51 csre52 csre53 csre54 csre55 csre56 csre57 +# csre58 csre59 csre5a csre5b csre5c csre5d csre5e csre5f +# csre60 csre61 csre62 csre63 csre64 csre65 csre66 csre67 +# csre68 csre69 csre6a csre6b csre6c csre6d csre6e csre6f +# csre70 csre71 csre72 csre73 csre74 csre75 csre76 csre77 +# csre78 csre79 csre7a csre7b csre7c csre7d csre7e csre7f ]; +#attach variables [ csr_E8 ] +# [ csre80 csre81 csre82 csre83 csre84 csre85 csre86 csre87 +# csre88 csre89 csre8a csre8b csre8c csre8d csre8e csre8f +# csre90 csre91 csre92 csre93 csre94 csre95 csre96 csre97 +# csre98 csre99 csre9a csre9b csre9c csre9d csre9e csre9f +# csrea0 csrea1 csrea2 csrea3 csrea4 csrea5 csrea6 csrea7 +# csrea8 csrea9 csreaa csreab csreac csread csreae csreaf +# csreb0 csreb1 csreb2 csreb3 csreb4 csreb5 csreb6 csreb7 +# csreb8 csreb9 csreba csrebb csrebc csrebd csrebe csrebf ]; +#attach variables [ csr_EC ] +# [ csrec0 csrec1 csrec2 csrec3 csrec4 csrec5 csrec6 csrec7 +# csrec8 csrec9 csreca csrecb csrecc csrecd csrece csrecf +# csred0 csred1 csred2 csred3 csred4 csred5 csred6 csred7 +# csred8 csred9 csreda csredb csredc csredd csrede csredf +# csree0 csree1 csree2 csree3 csree4 csree5 csree6 csree7 +# csree8 csree9 csreea csreeb csreec csreed csreee csreef +# csref0 csref1 csref2 csref3 csref4 csref5 csref6 csref7 +# csref8 csref9 csrefa csrefb csrefc csrefd csrefe csreff ]; +#attach variables [ csr_F0 ] +# [ csrf00 csrf01 csrf02 csrf03 csrf04 csrf05 csrf06 csrf07 +# csrf08 csrf09 csrf0a csrf0b csrf0c csrf0d csrf0e csrf0f +# csrf10 mvendorid marchid mimpid mhartid csrf15 csrf16 csrf17 +# csrf18 csrf19 csrf1a csrf1b csrf1c csrf1d csrf1e csrf1f +# csrf20 csrf21 csrf22 csrf23 csrf24 csrf25 csrf26 csrf27 +# csrf28 csrf29 csrf2a csrf2b csrf2c csrf2d csrf2e csrf2f +# csrf30 csrf31 csrf32 csrf33 csrf34 csrf35 csrf36 csrf37 +# csrf38 csrf39 csrf3a csrf3b csrf3c csrf3d csrf3e csrf3f +# csrf40 csrf41 csrf42 csrf43 csrf44 csrf45 csrf46 csrf47 +# csrf48 csrf49 csrf4a csrf4b csrf4c csrf4d csrf4e csrf4f +# csrf50 csrf51 csrf52 csrf53 csrf54 csrf55 csrf56 csrf57 +# csrf58 csrf59 csrf5a csrf5b csrf5c csrf5d csrf5e csrf5f +# csrf60 csrf61 csrf62 csrf63 csrf64 csrf65 csrf66 csrf67 +# csrf68 csrf69 csrf6a csrf6b csrf6c csrf6d csrf6e csrf6f +# csrf70 csrf71 csrf72 csrf73 csrf74 csrf75 csrf76 csrf77 +# csrf78 csrf79 csrf7a csrf7b csrf7c csrf7d csrf7e csrf7f ]; +#attach variables [ csr_F8 ] +# [ csrf80 csrf81 csrf82 csrf83 csrf84 csrf85 csrf86 csrf87 +# csrf88 csrf89 csrf8a csrf8b csrf8c csrf8d csrf8e csrf8f +# csrf90 csrf91 csrf92 csrf93 csrf94 csrf95 csrf96 csrf97 +# csrf98 csrf99 csrf9a csrf9b csrf9c csrf9d csrf9e csrf9f +# csrfa0 csrfa1 csrfa2 csrfa3 csrfa4 csrfa5 csrfa6 csrfa7 +# csrfa8 csrfa9 csrfaa csrfab csrfac csrfad csrfae csrfaf +# csrfb0 csrfb1 csrfb2 csrfb3 csrfb4 csrfb5 csrfb6 csrfb7 +# csrfb8 csrfb9 csrfba csrfbb csrfbc csrfbd csrfbe csrfbf ]; +#attach variables [ csr_FC ] +# [ csrfc0 csrfc1 csrfc2 csrfc3 csrfc4 csrfc5 csrfc6 csrfc7 +# csrfc8 csrfc9 csrfca csrfcb csrfcc csrfcd csrfce csrfcf +# csrfd0 csrfd1 csrfd2 csrfd3 csrfd4 csrfd5 csrfd6 csrfd7 +# csrfd8 csrfd9 csrfda csrfdb csrfdc csrfdd csrfde csrfdf +# csrfe0 csrfe1 csrfe2 csrfe3 csrfe4 csrfe5 csrfe6 csrfe7 +# csrfe8 csrfe9 csrfea csrfeb csrfec csrfed csrfee csrfef +# csrff0 csrff1 csrff2 csrff3 csrff4 csrff5 csrff6 csrff7 +# csrff8 csrff9 csrffa csrffb csrffc csrffd csrffe csrfff ]; + #TODO these names are madeup. do real ones exist? #TODO go through and use these instead of numbers @@ -177,6 +761,9 @@ aqrl: ".aqrl" is op2526=3 { export 3:$(XLEN); } crs1: cr0711 is cr0711 { export cr0711; } crs1: zero is cr0711 & zero & cop0711=0 { export 0:$(XLEN); } +crdNoSp: cd0711NoSp is cd0711NoSp { export cd0711NoSp; } +crdNoSp: zero is zero & cop0711=0 { export 0:$(XLEN); } + crd: cd0711 is cd0711 { export cd0711; } crd: zero is zero & cop0711=0 { export 0:$(XLEN); } @@ -254,117 +841,120 @@ csqspimm: uimm is cop0710 & cop1112 [ uimm = (cop0710 << 6) | (cop1112 << 4); ] # csr[11:10] - read/write (00, 01, 10) or read-only (11) # csr[9:8] - lowest privilege that can access the CSR -# 0x000-0x0ff -with csr: op3031=0 & op2829=0 { - : csr_0 is csr_0 { export csr_0; } # user, standard read/write -} - -# 0x100-0x1ff -with csr: op3031=0 & op2829=1 { - : csr_1 is csr_1 { export csr_1; } # supervisor, standard read/write -} - -# 0x200-0x2ff -with csr: op3031=0 & op2829=2 { - : csr_2 is csr_2 { export csr_2; } # hypervisor, standard read/write -} - -# 0x300-0x3ff -with csr: op3031=0 & op2829=3 { - : csr_3 is csr_3 { export csr_3; } # machine, standard read/write -} - -# 0x400-0x4ff -with csr: op3031=1 & op2829=0 { - : csr_4 is csr_4 { export csr_4; } # user, standard read/write -} - -# 0x500-0x5ff -with csr: op3031=1 & op2829=1 { - : csr_50 is csr_50 & op2727=0 { export csr_50; } # supervisor, standard read/write - : csr_58 is csr_58 & op2627=2 { export csr_58; } # supervisor, standard read/write - : csr_5C is csr_5C & op2627=3 { export csr_5C; } # supervisor, custom read/write -} - -# 0x600-0x6ff -with csr: op3031=1 & op2829=2 { - : csr_60 is csr_60 & op2727=0 { export csr_60; } # hypervisor, standard read/write - : csr_68 is csr_68 & op2627=2 { export csr_68; } # hypervisor, standard read/write - : csr_6C is csr_6C & op2627=3 { export csr_6C; } # hypervisor, custom read/write -} - -# 0x700-0x7ff -with csr: op3031=1 & op2829=3 { - : csr_70 is csr_70 & op2727=0 { export csr_70; } # machine, standard read/write - : csr_78 is csr_78 & op2527=4 { export csr_78; } # machine, standard read/write - : csr_7A is csr_7A & op2427=0xa { export csr_7A; } # machine, standard read/write debug - : csr_7B is csr_7B & op2427=0xb { export csr_7B; } # machine, debug-mode-only - : csr_7C is csr_7C & op2627=3 { export csr_7C; } # machine, custom read/write -} - -# 0x800-0x8ff -with csr: op3031=2 & op2829=0 { - : csr_8 is csr_8 { export csr_8; } # user, custom read/write -} - -# 0x900-0x9ff -with csr: op3031=2 & op2829=1 { - : csr_90 is csr_90 & op2727=0 { export csr_90; } # supervisor, standard read/write - : csr_98 is csr_98 & op2627=2 { export csr_98; } # supervisor, standard read/write - : csr_9C is csr_9C & op2627=3 { export csr_9C; } # supervisor, custom read/write -} - -# 0xa00-0xaff -with csr: op3031=2 & op2829=2 { - : csr_A0 is csr_A0 & op2727=0 { export csr_A0; } # hypervisor, standard read/write - : csr_A8 is csr_A8 & op2627=2 { export csr_A8; } # hypervisor, standard read/write - : csr_AC is csr_AC & op2627=3 { export csr_AC; } # hypervisor, custom read/write -} - -# 0xb00-0xbff -with csr: op3031=2 & op2829=3 { - : csr_B0 is csr_B0 & op2727=0 { export csr_B0; } # machine, standard read/write - : csr_B8 is csr_B8 & op2627=2 { export csr_B8; } # machine, standard read/write - : csr_BC is csr_BC & op2627=3 { export csr_BC; } # machine, custom read/write -} - -# 0xc00-0xcff -with csr: op3031=3 & op2829=0 { - : csr_C0 is csr_C0 & op2727=0 { export csr_C0; } # user, standard read-only - : csr_C8 is csr_C8 & op2627=2 { export csr_C8; } # user, standard read-only - : csr_CC is csr_CC & op2627=3 { export csr_CC; } # user, custom read-only -} +## 0x000-0x0ff +#with csr: op3031=0 & op2829=0 { +# : csr_0 is csr_0 { export csr_0; } # user, standard read/write +#} +# +## 0x100-0x1ff +#with csr: op3031=0 & op2829=1 { +# : csr_1 is csr_1 { export csr_1; } # supervisor, standard read/write +#} +# +## 0x200-0x2ff +#with csr: op3031=0 & op2829=2 { +# : csr_2 is csr_2 { export csr_2; } # hypervisor, standard read/write +#} +# +## 0x300-0x3ff +#with csr: op3031=0 & op2829=3 { +# : csr_3 is csr_3 { export csr_3; } # machine, standard read/write +#} +# +## 0x400-0x4ff +#with csr: op3031=1 & op2829=0 { +# : csr_4 is csr_4 { export csr_4; } # user, standard read/write +#} +# +## 0x500-0x5ff +#with csr: op3031=1 & op2829=1 { +# : csr_50 is csr_50 & op2727=0 { export csr_50; } # supervisor, standard read/write +# : csr_58 is csr_58 & op2627=2 { export csr_58; } # supervisor, standard read/write +# : csr_5C is csr_5C & op2627=3 { export csr_5C; } # supervisor, custom read/write +#} +# +## 0x600-0x6ff +#with csr: op3031=1 & op2829=2 { +# : csr_60 is csr_60 & op2727=0 { export csr_60; } # hypervisor, standard read/write +# : csr_68 is csr_68 & op2627=2 { export csr_68; } # hypervisor, standard read/write +# : csr_6C is csr_6C & op2627=3 { export csr_6C; } # hypervisor, custom read/write +#} +# +## 0x700-0x7ff +#with csr: op3031=1 & op2829=3 { +# : csr_70 is csr_70 & op2727=0 { export csr_70; } # machine, standard read/write +# : csr_78 is csr_78 & op2527=4 { export csr_78; } # machine, standard read/write +# : csr_7A is csr_7A & op2427=0xa { export csr_7A; } # machine, standard read/write debug +# : csr_7B is csr_7B & op2427=0xb { export csr_7B; } # machine, debug-mode-only +# : csr_7C is csr_7C & op2627=3 { export csr_7C; } # machine, custom read/write +#} +# +## 0x800-0x8ff +#with csr: op3031=2 & op2829=0 { +# : csr_8 is csr_8 { export csr_8; } # user, custom read/write +#} +# +## 0x900-0x9ff +#with csr: op3031=2 & op2829=1 { +# : csr_90 is csr_90 & op2727=0 { export csr_90; } # supervisor, standard read/write +# : csr_98 is csr_98 & op2627=2 { export csr_98; } # supervisor, standard read/write +# : csr_9C is csr_9C & op2627=3 { export csr_9C; } # supervisor, custom read/write +#} +# +## 0xa00-0xaff +#with csr: op3031=2 & op2829=2 { +# : csr_A0 is csr_A0 & op2727=0 { export csr_A0; } # hypervisor, standard read/write +# : csr_A8 is csr_A8 & op2627=2 { export csr_A8; } # hypervisor, standard read/write +# : csr_AC is csr_AC & op2627=3 { export csr_AC; } # hypervisor, custom read/write +#} +# +## 0xb00-0xbff +#with csr: op3031=2 & op2829=3 { +# : csr_B0 is csr_B0 & op2727=0 { export csr_B0; } # machine, standard read/write +# : csr_B8 is csr_B8 & op2627=2 { export csr_B8; } # machine, standard read/write +# : csr_BC is csr_BC & op2627=3 { export csr_BC; } # machine, custom read/write +#} +# +## 0xc00-0xcff +#with csr: op3031=3 & op2829=0 { +# : csr_C0 is csr_C0 & op2727=0 { export csr_C0; } # user, standard read-only +# : csr_C8 is csr_C8 & op2627=2 { export csr_C8; } # user, standard read-only +# : csr_CC is csr_CC & op2627=3 { export csr_CC; } # user, custom read-only +#} +# +## 0xd00-0xdff +#with csr: op3031=3 & op2829=1 { +# : csr_D0 is csr_D0 & op2727=0 { export csr_D0; } # supervisor, standard read-only +# : csr_D8 is csr_D8 & op2627=2 { export csr_D8; } # supervisor, standard read-only +# : csr_DC is csr_DC & op2627=3 { export csr_DC; } # supervisor, custom read-only +#} +# +## 0xe00-0xeff +#with csr: op3031=3 & op2829=2 { +# : csr_E0 is csr_E0 & op2727=0 { export csr_E0; } # hypervisor, standard read-only +# : csr_E8 is csr_E8 & op2627=2 { export csr_E8; } # hypervisor, standard read-only +# : csr_EC is csr_EC & op2627=3 { export csr_EC; } # hypervisor, custom read-only +#} +# +## 0xf00-0xfff +#with csr: op3031=3 & op2829=3 { +# : csr_F0 is csr_F0 & op2727=0 { export csr_F0; } # machine, standard read-only +# : csr_F8 is csr_F8 & op2627=2 { export csr_F8; } # machine, standard read-only +# : csr_FC is csr_FC & op2627=3 { export csr_FC; } # machine, custom read-only +#} +# + +csr: csr_reg is op2031 [ csr_reg = $(CSR_REG_START) + op2031; ] { export *[csreg]:$(XLEN) csr_reg; } -# 0xd00-0xdff -with csr: op3031=3 & op2829=1 { - : csr_D0 is csr_D0 & op2727=0 { export csr_D0; } # supervisor, standard read-only - : csr_D8 is csr_D8 & op2627=2 { export csr_D8; } # supervisor, standard read-only - : csr_DC is csr_DC & op2627=3 { export csr_DC; } # supervisor, custom read-only -} - -# 0xe00-0xeff -with csr: op3031=3 & op2829=2 { - : csr_E0 is csr_E0 & op2727=0 { export csr_E0; } # hypervisor, standard read-only - : csr_E8 is csr_E8 & op2627=2 { export csr_E8; } # hypervisor, standard read-only - : csr_EC is csr_EC & op2627=3 { export csr_EC; } # hypervisor, custom read-only -} - -# 0xf00-0xfff -with csr: op3031=3 & op2829=3 { - : csr_F0 is csr_F0 & op2727=0 { export csr_F0; } # machine, standard read-only - : csr_F8 is csr_F8 & op2627=2 { export csr_F8; } # machine, standard read-only - : csr_FC is csr_FC & op2627=3 { export csr_FC; } # machine, custom read-only -} - - - -vm: op2525 is op2525 { local tmp:1 = op2525; export tmp; } vs1: v1519 is v1519 { export v1519; } vs2: v2024 is v2024 { export v2024; } vs3: v0711 is v0711 { export v0711; } vd: v0711 is v0711 { export v0711; } +vm: ,v0^".t" is op2525=0 & v0 & vd { vd = vd & v0; } +vm: "" is op2525=1 { } + simm5: sop1519 is sop1519 { local tmp:$(XLEN) = sop1519; export tmp; } # zimm: op1519 is op1519 { local tmp:$(XLEN) = op1519; export tmp; } diff --git a/pypcode/processors/RISCV/data/languages/riscv32-fp.cspec b/pypcode/processors/RISCV/data/languages/riscv32-fp.cspec index d2dc4659..927b8ea4 100644 --- a/pypcode/processors/RISCV/data/languages/riscv32-fp.cspec +++ b/pypcode/processors/RISCV/data/languages/riscv32-fp.cspec @@ -17,11 +17,12 @@ - + + @@ -30,103 +31,178 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - - - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + - - - + + + - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/RISCV/data/languages/riscv32.cspec b/pypcode/processors/RISCV/data/languages/riscv32.cspec index 4a08e655..5f820af9 100644 --- a/pypcode/processors/RISCV/data/languages/riscv32.cspec +++ b/pypcode/processors/RISCV/data/languages/riscv32.cspec @@ -15,11 +15,12 @@ - + + @@ -28,43 +29,64 @@ - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - + + + + + + + + + + + + + + + + + + + + - + - + + + + + @@ -83,6 +105,24 @@ + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/RISCV/data/languages/riscv64-fp.cspec b/pypcode/processors/RISCV/data/languages/riscv64-fp.cspec index 329cb033..fd17e478 100644 --- a/pypcode/processors/RISCV/data/languages/riscv64-fp.cspec +++ b/pypcode/processors/RISCV/data/languages/riscv64-fp.cspec @@ -22,6 +22,7 @@ + @@ -30,103 +31,178 @@ - + - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - - - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + - - + + - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/RISCV/data/languages/riscv64.cspec b/pypcode/processors/RISCV/data/languages/riscv64.cspec index 1fe4fe3f..90970af9 100644 --- a/pypcode/processors/RISCV/data/languages/riscv64.cspec +++ b/pypcode/processors/RISCV/data/languages/riscv64.cspec @@ -18,45 +18,65 @@ + + + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + + + + - - + + - - - + + + + + + + + + + + + + + + + + @@ -65,6 +85,10 @@ + + + + @@ -83,6 +107,24 @@ + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/SuperH/data/languages/superh.sinc b/pypcode/processors/SuperH/data/languages/superh.sinc index a3428342..44c9fdef 100644 --- a/pypcode/processors/SuperH/data/languages/superh.sinc +++ b/pypcode/processors/SuperH/data/languages/superh.sinc @@ -2307,8 +2307,7 @@ define pcodeop Sleep_Standby; :bclr "#"imm3_00_02, rn_04_07 is opcode_08_15=0b10000110 & rn_04_07 & opcode_03_03=0b0 & imm3_00_02 { - local b = *:1 (rn_04_07); - *:1 (rn_04_07) = b & (~(1 << imm3_00_02)); + rn_04_07 = rn_04_07 & (~(1 << imm3_00_02)); } # BLD.B #imm3, @(disp12,Rn) 0011nnnn0iii1001 0011dddddddddddd (imm of (disp+Rn)) → T diff --git a/pypcode/processors/SuperH4/data/languages/SuperH4.sinc b/pypcode/processors/SuperH4/data/languages/SuperH4.sinc index 372fe95b..1b0e76cd 100644 --- a/pypcode/processors/SuperH4/data/languages/SuperH4.sinc +++ b/pypcode/processors/SuperH4/data/languages/SuperH4.sinc @@ -346,9 +346,9 @@ define token instr(16) N_1 = ( 9,11) # register id N_2 = (10,11) # register id FRN_0 = ( 8,11) # float register id - FRN_1 = ( 8,10) # float register id - FRN_2 = ( 8,10) # float register id - DRN_0 = ( 8,10) # double register id + FRN_1 = ( 9,11) # float register id + FRN_2 = ( 9,11) # float register id + DRN_0 = ( 9,11) # double register id DRN_1 = ( 9,11) # double register id XDN_1 = ( 9,11) # double register id XDRN = ( 8,11) # float register id diff --git a/pypcode/processors/SuperH4/data/languages/SuperH4_le.cspec b/pypcode/processors/SuperH4/data/languages/SuperH4_le.cspec index 92dc5b39..89930578 100644 --- a/pypcode/processors/SuperH4/data/languages/SuperH4_le.cspec +++ b/pypcode/processors/SuperH4/data/languages/SuperH4_le.cspec @@ -29,30 +29,30 @@ - - - - + - + - + + + + diff --git a/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc b/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc index da9608a9..a8d8d82c 100644 --- a/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc +++ b/pypcode/processors/Xtensa/data/languages/xtensaArch.sinc @@ -120,7 +120,7 @@ define token insn(24) # Signed and unsigned immediates. Named [us]N_L.M, where u and s denote signedness, L and M the # least and most significant bit of the immediate in the instruction word, and N the length # (i.e. M-L+1). - u3_21_23 = (0,2) + u3_21_23 = (1,3) u4_20_23 = (0,3) s8_16_23 = (0,7) signed u8_16_23 = (0,7) @@ -128,31 +128,32 @@ define token insn(24) s12_12_23 = (0,11) signed u16_8_23 = (0,15) s8_6_23 = (0,17) signed - u1_20 = (3,3) + u1_20 = (0,0) u2_18_19 = (4,5) - u3_17_19 = (4,6) + u3_17_19 = (5,7) u2_16_17 = (6,7) - u1_16 = (7,7) - u1_15_15 = (8,8) - u2_14_15 = (8,9) - u3_13_15 = (8,10) + u1_16 = (4,4) + u1_15_15 = (11,11) + u2_14_15 = (10,11) + u3_13_15 = (9,11) u4_12_15 = (8,11) - m0m1_14_14 = (9,9) - u2_12_13 = (10,11) - mw_12_13 = (10,11) - u1_12 = (11,11) + m0m1_14_14 = (10,10) + u2_12_13 = (8,9) + mw_12_13 = (8,9) + u1_12 = (8,8) u4_8_11 = (12,15) u8_4_11 = (12,19) s4_8_11 = (12,15) signed - u1_7_7 = (16,16) + u1_7_7 = (19,19) u2_6_7 = (16,17) - u3_5_7 = (16,18) + u3_5_7 = (17,19) u4_4_7 = (16,19) s4_4_7 = (16,19) - m2m3_6_6 = (17,17) + m2m3_6_6 = (18,18) u_4_23 = (0,19) + t2_4_5 = (16,17) u2_4_5 = (18,19) - u1_4 = (19,19) + u1_4 = (16,16) ; # little-endian -> big-endian 16-bit conversion chart @@ -169,11 +170,11 @@ define token narrowinsn(16) n_u4_12_15 = (0,3) n_s4_12_15 = (0,3) signed n_u4_8_11 = (4,7) - n_u1_7 = (8,8) - n_u2_6_7 = (8,9) + n_u1_7 = (11,11) + n_u2_6_7 = (10,11) n_u4_4_7 = (8,11) - n_s3_4_6 = (9,11) - n_u2_4_5 = (10,11) + n_s3_4_6 = (8,10) + n_u2_4_5 = (8,9) ; @else @@ -228,6 +229,7 @@ define token insn(24) s4_4_7 = (4,7) m2m3_6_6 = (6,6) u_4_23 = (4,23) + t2_4_5 = (4,5) u2_4_5 = (4,5) u1_4 = (4,4) ; diff --git a/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc b/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc index 71e23ce2..f7e2d391 100644 --- a/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc +++ b/pypcode/processors/Xtensa/data/languages/xtensaInstructions.sinc @@ -1462,7 +1462,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } # MUL.AD.* - Signed Multiply, pg. 432. -:mul.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x4 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as:2; tm2:2 = m2m3_6_6:2; M1 = zext(tm1); @@ -1470,21 +1470,21 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x5 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as(2); tm2:2 = m2m3_6_6:2; M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x6 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as:2; tm2:2 = m2m3_6_6(2); M1 = zext(tm1); M2 = zext(tm2); ACC = sext(M1:2) * sext(M2:2); } -:mul.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0x7 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as(2); tm2:2 = m2m3_6_6(2); M1 = zext(tm1); @@ -1526,7 +1526,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } # MUL.AD.* - Signed Multiply, pg. 434. -:mul.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x4 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x4 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6:2; M1 = zext(tm1); @@ -1534,7 +1534,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x5 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x5 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6:2; M1 = zext(tm1); @@ -1542,7 +1542,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x6 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x6 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6(2); M1 = zext(tm1); @@ -1550,7 +1550,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = sext(M1:2) * sext(M2:2); } -:mul.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x7 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mul.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x7 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6(2); M1 = zext(tm1); @@ -1590,7 +1590,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.ll as, m2m3_6_6 is op2 = 0x3 & op1 = 0x8 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as:2; tm2:2 = m2m3_6_6:2; M1 = zext(tm1); @@ -1598,21 +1598,21 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.hl as, m2m3_6_6 is op2 = 0x3 & op1 = 0x9 & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as(2); tm2:2 = m2m3_6_6:2; M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xa & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.lh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xa & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as:2; tm2:2 = m2m3_6_6(2); M1 = zext(tm1); M2 = zext(tm2); ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xb & ar = 0 & as & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.ad.hh as, m2m3_6_6 is op2 = 0x3 & op1 = 0xb & ar = 0 & as & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = as(2); tm2:2 = m2m3_6_6(2); M1 = zext(tm1); @@ -1652,7 +1652,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x8 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.ll m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x8 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6:2; M1 = zext(tm1); @@ -1660,7 +1660,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x9 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hl m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0x9 & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6:2; M1 = zext(tm1); @@ -1668,7 +1668,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xa & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.lh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xa & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6(2); M1 = zext(tm1); @@ -1676,7 +1676,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist ACC = ACC + (sext(M1:2) * sext(M2:2)); } -:mula.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xb & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hh m0m1_14_14, m2m3_6_6 is op2 = 0x2 & op1 = 0xb & ar = 0 & u1_15_15 = 0 & u2_12_13 = 0 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6(2); M1 = zext(tm1); @@ -1775,7 +1775,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } # Signed Mult/Accum, Ld/Autodec MULA.DD.*.LDDEC, pg. 446. -:mula.dd.ll.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { +:mula.dd.ll.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & op0 = 0x4 { local vaddr:4 = as - 4; tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6:2; @@ -1786,7 +1786,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist mw_12_13 = *:4 vaddr; } -:mula.dd.hl.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hl.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { local vaddr:4 = as - 4; tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6(2); @@ -1797,7 +1797,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist mw_12_13 = *:4 vaddr; } -:mula.dd.lh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.lh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { local vaddr:4 = as - 4; tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6:2; @@ -1808,7 +1808,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist mw_12_13 = *:4 vaddr; } -:mula.dd.hh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.dd.hh.lddec mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x1 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { local vaddr:4 = as - 4; tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6(2); @@ -1820,7 +1820,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist } # Signed Mult/Accum, Ld/Autoinc MULA.DD.*.LDINC, pg. 448. -:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.ll.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x8 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { local vaddr:4 = as + 4; tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6:2; @@ -1831,7 +1831,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist mw_12_13 = *:4 vaddr; } -:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.hl.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0x9 & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { local vaddr:4 = as + 4; tm1:2 = m0m1_14_14:2; tm2:2 = m2m3_6_6(2); @@ -1842,7 +1842,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist mw_12_13 = *:4 vaddr; } -:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.lh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xa & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { local vaddr:4 = as + 4; tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6:2; @@ -1853,7 +1853,7 @@ rfi_eps: ptr is u4_8_11 [ ptr = $(EPS_BASE) + (4 * u4_8_11); ] { export *[regist mw_12_13 = *:4 vaddr; } -:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & u2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { +:mula.da.hh.ldinc mw_12_13, as, m0m1_14_14, m2m3_6_6 is op2 = 0x0 & op1 = 0xb & as & u1_15_15 = 0 & mw_12_13 & m0m1_14_14 & u1_7_7 = 0 & t2_4_5 = 0 & m2m3_6_6 & op0 = 0x4 { local vaddr:4 = as + 4; tm1:2 = m0m1_14_14(2); tm2:2 = m2m3_6_6(2); diff --git a/pypcode/processors/eBPF/data/languages/eBPF.sinc b/pypcode/processors/eBPF/data/languages/eBPF.sinc index dd0e7417..62a77a10 100644 --- a/pypcode/processors/eBPF/data/languages/eBPF.sinc +++ b/pypcode/processors/eBPF/data/languages/eBPF.sinc @@ -17,7 +17,9 @@ define register offset=0 size=8 [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 P # Instruction encoding: Insop:8, dst_reg:4, src_reg:4, off:16, imm:32 - from lsb to msb @if ENDIAN == "little" define token instr(64) + llvm_imm_callx_zero=(36, 63) imm=(32, 63) signed + llvm_reg_callx=(32, 35) # special encoding for callx instruction emitted by LLVM off=(16, 31) signed src=(12, 15) dst=(8, 11) @@ -35,6 +37,8 @@ define token immtoken(64) @else # ENDIAN == "big" define token instr(64) imm=(0, 31) signed + llvm_reg_callx=(0, 3) # special encoding for callx instruction emitted by LLVM + llvm_imm_callx_zero=(4, 31) off=(32, 47) signed src=(48, 51) dst=(52, 55) @@ -51,7 +55,7 @@ define token immtoken(64) @endif # ENDIAN = "big" #To operate with registers -attach variables [ src dst ] [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 _ _ _ _ _ ]; +attach variables [ src dst llvm_reg_callx ] [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 _ _ _ _ _ ]; #Arithmetic instructions #BPF_ALU64 @@ -435,4 +439,20 @@ disp32: reloc is imm [ reloc = inst_next + imm * 8; ] { export *:4 reloc; } call disp32; } +# GCC encoding and LLVM 19.1+ encoding +:CALLX dst is op_alu_jmp_opcode=0x8 & op_alu_jmp_source=1 & op_insn_class=0x5 & src=0 & imm=0 & dst { + call [dst]; +} + +# LLVM encoding used until LLVM 19.1 +# Introduced in https://github.com/llvm/llvm-project/commit/9a67245d881f4cf89fd8f897ae2cd0bccec49496 +# Modified in https://github.com/llvm/llvm-project/commit/c43ad6c0fddac0bbed5e881801dd2bc2f9eeba2d +:CALLX llvm_reg_callx is op_alu_jmp_opcode=0x8 & op_alu_jmp_source=1 & op_insn_class=0x5 & dst=0 & src=0 & llvm_imm_callx_zero=0 & llvm_reg_callx { + call [llvm_reg_callx]; +} +# Both CALLX encodings are matched when both dst and imm are zero +:CALLX R0 is op_alu_jmp_opcode=0x8 & op_alu_jmp_source=1 & op_insn_class=0x5 & dst=0 & src=0 & imm=0 & R0 { + call [R0]; +} + :EXIT is op_alu_jmp_opcode=0x9 & op_alu_jmp_source=0 & op_insn_class=0x5 { return [*:8 R10]; } diff --git a/pypcode/processors/x86/data/extensions/rust/unix32/cc.xml b/pypcode/processors/x86/data/extensions/rust/unix32/cc.xml new file mode 100644 index 00000000..4a7b38b0 --- /dev/null +++ b/pypcode/processors/x86/data/extensions/rust/unix32/cc.xml @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pypcode/processors/x86/data/extensions/rust/unix/probe_fixup.xml b/pypcode/processors/x86/data/extensions/rust/unix32/probe_fixup.xml similarity index 100% rename from pypcode/processors/x86/data/extensions/rust/unix/probe_fixup.xml rename to pypcode/processors/x86/data/extensions/rust/unix32/probe_fixup.xml diff --git a/pypcode/processors/x86/data/extensions/rust/unix32/try_fixup.xml b/pypcode/processors/x86/data/extensions/rust/unix32/try_fixup.xml new file mode 100644 index 00000000..1d7cbcca --- /dev/null +++ b/pypcode/processors/x86/data/extensions/rust/unix32/try_fixup.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/pypcode/processors/x86/data/extensions/rust/unix/cc.xml b/pypcode/processors/x86/data/extensions/rust/unix64/cc.xml similarity index 100% rename from pypcode/processors/x86/data/extensions/rust/unix/cc.xml rename to pypcode/processors/x86/data/extensions/rust/unix64/cc.xml diff --git a/pypcode/processors/x86/data/extensions/rust/windows/probe_fixup.xml b/pypcode/processors/x86/data/extensions/rust/unix64/probe_fixup.xml similarity index 100% rename from pypcode/processors/x86/data/extensions/rust/windows/probe_fixup.xml rename to pypcode/processors/x86/data/extensions/rust/unix64/probe_fixup.xml diff --git a/pypcode/processors/x86/data/extensions/rust/unix/try_fixup.xml b/pypcode/processors/x86/data/extensions/rust/unix64/try_fixup.xml similarity index 100% rename from pypcode/processors/x86/data/extensions/rust/unix/try_fixup.xml rename to pypcode/processors/x86/data/extensions/rust/unix64/try_fixup.xml diff --git a/pypcode/processors/x86/data/extensions/rust/windows32/probe_fixup.xml b/pypcode/processors/x86/data/extensions/rust/windows32/probe_fixup.xml new file mode 100644 index 00000000..9bb5fd09 --- /dev/null +++ b/pypcode/processors/x86/data/extensions/rust/windows32/probe_fixup.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/pypcode/processors/x86/data/extensions/rust/windows32/try_fixup.xml b/pypcode/processors/x86/data/extensions/rust/windows32/try_fixup.xml new file mode 100644 index 00000000..ecb17a9f --- /dev/null +++ b/pypcode/processors/x86/data/extensions/rust/windows32/try_fixup.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/pypcode/processors/x86/data/extensions/rust/windows64/probe_fixup.xml b/pypcode/processors/x86/data/extensions/rust/windows64/probe_fixup.xml new file mode 100644 index 00000000..9bb5fd09 --- /dev/null +++ b/pypcode/processors/x86/data/extensions/rust/windows64/probe_fixup.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/pypcode/processors/x86/data/extensions/rust/windows/try_fixup.xml b/pypcode/processors/x86/data/extensions/rust/windows64/try_fixup.xml similarity index 100% rename from pypcode/processors/x86/data/extensions/rust/windows/try_fixup.xml rename to pypcode/processors/x86/data/extensions/rust/windows64/try_fixup.xml diff --git a/pypcode/processors/x86/data/languages/ia.sinc b/pypcode/processors/x86/data/languages/ia.sinc index 602f675c..d216d902 100644 --- a/pypcode/processors/x86/data/languages/ia.sinc +++ b/pypcode/processors/x86/data/languages/ia.sinc @@ -4894,13 +4894,13 @@ define pcodeop verw; # of this instruction is always 64-bits and is always in memory". Is it an error that the "Instruction" entry in the # box giving the definition does not specify m64? :VMPTRST m64 is vexMode=0 & byte=0x0f; byte=0xc7; ( mod != 0b11 & reg_opcode=7 ) ... & m64 { vmptrst(m64); } -:VMREAD rm32, Reg32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0x78; rm32 & check_rm32_dest ... & Reg32 ... { rm32 = vmread(Reg32); build check_rm32_dest; } +:VMREAD rm32, Reg32 is $(PRE_NO) & vexMode=0 & opsize=1 & byte=0x0f; byte=0x78; rm32 & check_rm32_dest ... & Reg32 ... { rm32 = vmread(Reg32); build check_rm32_dest; } @ifdef IA64 -:VMREAD rm64, Reg64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x78; rm64 & Reg64 ... { rm64 = vmread(Reg64); } +:VMREAD rm64, Reg64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x78; rm64 & Reg64 ... { rm64 = vmread(Reg64); } @endif -:VMWRITE Reg32, rm32 is vexMode=0 & opsize=1 & byte=0x0f; byte=0x79; rm32 & Reg32 ... & check_Reg32_dest ... { vmwrite(rm32,Reg32); build check_Reg32_dest; } +:VMWRITE Reg32, rm32 is $(PRE_NO) & vexMode=0 & opsize=1 & byte=0x0f; byte=0x79; rm32 & Reg32 ... & check_Reg32_dest ... { vmwrite(rm32,Reg32); build check_Reg32_dest; } @ifdef IA64 -:VMWRITE Reg64, rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x79; rm64 & Reg64 ... { vmwrite(rm64,Reg64); } +:VMWRITE Reg64, rm64 is $(LONGMODE_ON) & $(PRE_NO) & vexMode=0 & opsize=2 & byte=0x0f; byte=0x79; rm64 & Reg64 ... { vmwrite(rm64,Reg64); } @endif :VMXOFF is vexMode=0 & byte=0x0f; byte=0x01; byte=0xc4 { vmxoff(); } # NB: this opcode is incorrect in the 2005 edition of the Intel manual. Opcode below is taken from the 2008 version. @@ -10457,4 +10457,46 @@ define pcodeop PackedSwapDWords; define pcodeop MaskedMoveQWord; :MASKMOVQ mmxreg1, mmxreg2 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xF7; mmxmod = 3 & mmxreg1 & mmxreg2 { mmxreg1 = MaskedMoveQWord(mmxreg1, mmxreg2); } + +#### +#### SSE4a instructions +#### + +bitLen: val is imm8 [ val=imm8 & 0x3f; ] { export *[const]:1 val; } +lsbOffset: val is imm8 [ val=imm8 & 0x3f; ] { export *[const]:1 val; } +:EXTRQ XmmReg2, bitLen, lsbOffset is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x78; reg_opcode=0 & XmmReg2; bitLen; lsbOffset { + local mask:16 = ((1 << bitLen) - 1) << lsbOffset; + local val:16 = (XmmReg2 & mask) >> lsbOffset; + XmmReg2 = val; +} + +:EXTRQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_66) & byte=0x0F; byte=0x79; XmmReg1 & XmmReg2 { + local len = XmmReg2[0,6]; + local offs = XmmReg2[6,6]; + local mask = ((1 << len) - 1) << offs; + local val = (XmmReg1 & mask) >> offs; + XmmReg1 = val; +} + +:INSERTQ XmmReg1, XmmReg2, bitLen, lsbOffset is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x78; XmmReg1 & XmmReg2; bitLen; lsbOffset { + local mask:16 = ((1 << bitLen) - 1) << lsbOffset; + local val:16 = (zext(XmmReg2[0,64]) & ((1 << bitLen) - 1)); + XmmReg1 = (XmmReg1 & ~zext(mask)) | (zext(val) << lsbOffset); +} + +:INSERTQ XmmReg1, XmmReg2 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x79; XmmReg1 & XmmReg2 { + local len = XmmReg2[64,6]; + local offs = XmmReg2[72,6]; + local mask:16 = ((1 << len) - 1) << offs; + local val:16 = (zext(XmmReg2[0,64]) & ((1 << len) - 1)); + XmmReg1 = (XmmReg1 & ~zext(mask)) | (zext(val) << offs); +} + +:MOVNTSD m64, XmmReg1 is vexMode=0 & $(PRE_F2) & byte=0x0F; byte=0x2B; XmmReg1 ... & m64 { + m64 = XmmReg1[0,64]; +} + +:MOVNTSS m32, XmmReg1 is vexMode=0 & $(PRE_F3) & byte=0x0F; byte=0x2B; XmmReg1 ... & m32 { + m32 = XmmReg1[0,32]; +} } # end with : lockprefx=0 diff --git a/pypcode/processors/x86/data/languages/x86-64-win.cspec b/pypcode/processors/x86/data/languages/x86-64-win.cspec index 846134c1..5310d4e1 100644 --- a/pypcode/processors/x86/data/languages/x86-64-win.cspec +++ b/pypcode/processors/x86/data/languages/x86-64-win.cspec @@ -233,4 +233,13 @@ ]]> + + + + + + + diff --git a/pypcode/processors/x86/data/languages/x86-64.dwarf b/pypcode/processors/x86/data/languages/x86-64.dwarf index c8218184..8e4e3979 100644 --- a/pypcode/processors/x86/data/languages/x86-64.dwarf +++ b/pypcode/processors/x86/data/languages/x86-64.dwarf @@ -30,5 +30,24 @@ + + + + + + + diff --git a/pypcode/processors/x86/data/languages/x86.dwarf b/pypcode/processors/x86/data/languages/x86.dwarf index 154617ec..3877fd1f 100644 --- a/pypcode/processors/x86/data/languages/x86.dwarf +++ b/pypcode/processors/x86/data/languages/x86.dwarf @@ -30,5 +30,24 @@ + + + + + + + diff --git a/pypcode/processors/x86/data/languages/x86gcc.cspec b/pypcode/processors/x86/data/languages/x86gcc.cspec index 839c0fe8..1bc77422 100644 --- a/pypcode/processors/x86/data/languages/x86gcc.cspec +++ b/pypcode/processors/x86/data/languages/x86gcc.cspec @@ -381,6 +381,17 @@ + + + + + + + + diff --git a/pypcode/processors/x86/data/languages/x86win.cspec b/pypcode/processors/x86/data/languages/x86win.cspec index d7598226..19c6a287 100644 --- a/pypcode/processors/x86/data/languages/x86win.cspec +++ b/pypcode/processors/x86/data/languages/x86win.cspec @@ -386,4 +386,13 @@ ]]> + + + + + + + diff --git a/pypcode/processors/x86/data/patterns/prepatternconstraints.xml b/pypcode/processors/x86/data/patterns/prepatternconstraints.xml index ea92c2ab..51d98bbe 100644 --- a/pypcode/processors/x86/data/patterns/prepatternconstraints.xml +++ b/pypcode/processors/x86/data/patterns/prepatternconstraints.xml @@ -7,6 +7,15 @@ x86win_prepatterns.xml + + x86gcc_prepatterns.xml + - + + + + x86gcc_prepatterns.xml + + + diff --git a/pypcode/processors/x86/data/patterns/x86-64gcc_patterns.xml b/pypcode/processors/x86/data/patterns/x86-64gcc_patterns.xml index 2daa852e..9c70076c 100644 --- a/pypcode/processors/x86/data/patterns/x86-64gcc_patterns.xml +++ b/pypcode/processors/x86/data/patterns/x86-64gcc_patterns.xml @@ -48,11 +48,70 @@ 0x41564155 0x41554154 0x41 010101.. 0100100. 0x89 11...... 0x55 - 0x41 010101.. 0x41 010101.. 0100100. 0x89 11...... + + + + 0xf3 0x0f 0x1e 0xfa 0x48 0x89 0x5c 0x24 11...000 0x48 0x89 0x6c 0x24 11...000 + 0xf3 0x0f 0x1e 0xfa 0x48 0x89 0x5c 0x24 11...000 0x4c 0x89 0x64 0x24 111..000 + 0xf3 0x0f 0x1e 0xfa 0x48 0x89 0x6c 0x24 11...000 0x4c 0x89 0x64 0x24 111..000 + 0xf3 0x0f 0x1e 0xfa 0x5589e5 + 0xf3 0x0f 0x1e 0xfa 0x554889e5 + 0xf3 0x0f 0x1e 0xfa 0x534889fb + 0xf3 0x0f 0x1e 0xfa 0x554889fd + 0xf3 0x0f 0x1e 0xfa 0x534889fb + 0xf3 0x0f 0x1e 0xfa 0x53 0x48 0x83 0xec 0....000 + 0xf3 0x0f 0x1e 0xfa 0x53 0x48 0x81 0xec .....000 00...... 0x00 + + 0xf3 0x0f 0x1e 0xfa 0x55 0x48 0x89 0xe5 0x48 100000.1 0xec .....000 + 0xf3 0x0f 0x1e 0xfa 0x554889e553 + 0xf3 0x0f 0x1e 0xfa 0x554889fd53 + 0xf3 0x0f 0x1e 0xfa 0x554889e548897df8 + 0xf3 0x0f 0x1e 0xfa 0x53 0x48 0x89 0xfb 0xe8 ........ ........ 0xff 0xff + 0xf3 0x0f 0x1e 0xfa 0x4154 0x55 0100100. 0x89 11...... + 0xf3 0x0f 0x1e 0xfa 0x4154 0x55 0x53 0100100. 0x89 11...... + + 0xf3 0x0f 0x1e 0xfa 0x415741564155 + 0xf3 0x0f 0x1e 0xfa 0x41564155 + 0xf3 0x0f 0x1e 0xfa 0x41554154 + 0xf3 0x0f 0x1e 0xfa 0x41 010101.. 0100100. 0x89 11...... 0x55 + 0xf3 0x0f 0x1e 0xfa 0x41 010101.. 0x41 010101.. 0100100. 0x89 11...... + + + + 0x90 0x90 + 0xc3 0x90 + 0x6690 + 0xc9 0xc3 + 0xe9........ + 0xe9........90 + 0xeb.. + 0xeb..90 + 0x5d 0xc3 + 0x5b 0xc3 + 0x41 010111.. 0xc3 + 0x31c0 0xc3 + 0x4883c4 ....1000 0xc3 + 0x666690 + 0x0f1f00 + 0x0f1f4000 + 0x0f1f440000 + 0x660f1f440000 + 0x0f1f8000000000 + 0x0f1f840000000000 + 0x660f1f840000000000 + + + 0xf3 0x0f 0x1e 0xfa + + + + + 0x5589e5 diff --git a/pypcode/processors/x86/data/patterns/x86-64win_patterns.xml b/pypcode/processors/x86/data/patterns/x86-64win_patterns.xml index 50b144af..0b3d2829 100644 --- a/pypcode/processors/x86/data/patterns/x86-64win_patterns.xml +++ b/pypcode/processors/x86/data/patterns/x86-64win_patterns.xml @@ -89,4 +89,17 @@ 0xcccc * 0x4c8b 11...100 01001.01 0x89 + + + 01001... 0x3b 0x0d ........ ........ ........ ........ + 0x75 0x10 + 01001... 0xc1 0xc1 0x10 + 0x66 0xf7 0xc1 0xff 0xff + 0x75 0x01 + 0xc3 + 01001... 0xc1 0xc9 0x10 + 0xe9 + + + diff --git a/pypcode/processors/x86/data/patterns/x86gcc_patterns.xml b/pypcode/processors/x86/data/patterns/x86gcc_patterns.xml index 89885e5a..fd06503c 100644 --- a/pypcode/processors/x86/data/patterns/x86gcc_patterns.xml +++ b/pypcode/processors/x86/data/patterns/x86gcc_patterns.xml @@ -108,9 +108,35 @@ 0x5589e5 0x8d 0x4c ..100100 0x04 0x83 0xe4 0xf. 0x57 0x8d 0x7c ..100100 0x08 0x83 0xe4 0xf. + + + 0xf3 0x0f 0x1e 0xfb 0x5589e5 + 0xf3 0x0f 0x1e 0xfb 0x8d 0x4c ..100100 0x04 0x83 0xe4 0xf. + 0xf3 0x0f 0x1e 0xfb 0x57 0x8d 0x7c ..100100 0x08 0x83 0xe4 0xf. + + + + 0x90 + 0xc3 + 0xe9........ + 0xeb.. + 0x89f6 + 0x8d7600 + 0x8d742600 + 0x8db600000000 + 0x8dbf00000000 + 0x8dbc2700000000 + 0x8db42600000000 + + + 0xf3 0x0f 0x1e 0xfb + + + + diff --git a/pypcode/processors/x86/data/patterns/x86gcc_prepatterns.xml b/pypcode/processors/x86/data/patterns/x86gcc_prepatterns.xml new file mode 100644 index 00000000..84b6d20d --- /dev/null +++ b/pypcode/processors/x86/data/patterns/x86gcc_prepatterns.xml @@ -0,0 +1,20 @@ + + + + + 0xff25........ + 0x68......00 + 0xe9......ff + + + + + + + 0xf3 0x0f 0x1e 0xfa + 0xf2 0xff 0x25 + + + + + diff --git a/pypcode/processors/x86/data/patterns/x86win_patterns.xml b/pypcode/processors/x86/data/patterns/x86win_patterns.xml index 4c4b59e7..c048c9f3 100644 --- a/pypcode/processors/x86/data/patterns/x86win_patterns.xml +++ b/pypcode/processors/x86/data/patterns/x86win_patterns.xml @@ -144,4 +144,13 @@ + + 0x3b 0x0d 0x.. 0x.. 0x.. 0x.. + 0x75 0x01 + 0xc3 + 0xe9 + + + + diff --git a/pypcode/sleigh/Makefile b/pypcode/sleigh/Makefile index 02af4787..5330c157 100644 --- a/pypcode/sleigh/Makefile +++ b/pypcode/sleigh/Makefile @@ -79,8 +79,8 @@ EXTERNAL_CONSOLEEXT_NAMES=$(subst .cc,,$(notdir $(EXTERNAL_CONSOLEEXT_SOURCE))) CORE= xml marshal space float address pcoderaw translate opcodes globalcontext # Additional core files for any projects that decompile DECCORE=capability architecture options graph cover block cast typeop database cpool \ - comment stringmanage modelrules fspec action loadimage grammar varnode op \ - type variable varmap jumptable emulate emulateutil flow userop multiprecision \ + comment stringmanage modelrules fspec action loadimage grammar varnode op type \ + variable varmap jumptable emulate emulateutil flow userop expression multiprecision \ funcdata funcdata_block funcdata_op funcdata_varnode unionresolve pcodeinject \ heritage prefersplit rangeutil ruleaction subflow blockaction merge double \ transform constseq coreaction condexe override dynamic crc32 prettyprint \ @@ -99,7 +99,7 @@ SPECIAL=consolemain sleighexample test # Any additional modules for the command line decompiler EXTRA= $(filter-out $(CORE) $(DECCORE) $(SLEIGH) $(GHIDRA) $(SLACOMP) $(SPECIAL),$(ALL_NAMES)) -EXECS=decomp_dbg decomp_opt ghidra_test_dbg ghidra_dbg ghidra_opt sleigh_dbg sleigh_opt libdecomp_dbg.a libdecomp.a +EXECS=decomp_dbg decomp_opt decomp_test_dbg ghidra_dbg ghidra_opt sleigh_dbg sleigh_opt libdecomp_dbg.a libdecomp.a # Possible conditional compilation flags # __TERMINAL__ # Turn on terminal support for console mode @@ -191,7 +191,7 @@ endif ifeq ($(MAKECMDGOALS),decomp_opt) DEPNAMES=com_opt/depend endif -ifneq (,$(filter $(MAKECMDGOALS),ghidra_test_dbg test)) +ifneq (,$(filter $(MAKECMDGOALS),decomp_test_dbg test)) DEPNAMES=test_dbg/depend endif ifeq ($(MAKECMDGOALS),reallyclean) @@ -253,11 +253,12 @@ decomp_dbg: $(COMMANDLINE_DBG_OBJS) decomp_opt: $(COMMANDLINE_OPT_OBJS) $(CXX) $(OPT_CXXFLAGS) $(ARCH_TYPE) -o decomp_opt $(COMMANDLINE_OPT_OBJS) $(BFDLIB) $(LNK) -ghidra_test_dbg: $(TEST_DEBUG_OBJS) - $(CXX) $(DBG_CXXFLAGS) $(ARCH_TYPE) -o ghidra_test_dbg $(TEST_DEBUG_OBJS) $(BFDLIB) $(LNK) +#decomp_test_dbg: DBG_CXXFLAGS += -D_GLIBCXX_ASSERTIONS -fsanitize=address,undefined +decomp_test_dbg: $(TEST_DEBUG_OBJS) + $(CXX) $(DBG_CXXFLAGS) $(ARCH_TYPE) -o decomp_test_dbg $(TEST_DEBUG_OBJS) $(BFDLIB) $(LNK) -test: ghidra_test_dbg - ./ghidra_test_dbg +test: decomp_test_dbg + ./decomp_test_dbg ghidra_dbg: $(GHIDRA_DBG_OBJS) $(CXX) $(DBG_CXXFLAGS) $(ADDITIONAL_FLAGS) $(MAKE_STATIC) $(ARCH_TYPE) -o ghidra_dbg $(GHIDRA_DBG_OBJS) diff --git a/pypcode/sleigh/address.cc b/pypcode/sleigh/address.cc index dae7f132..9e8039d4 100644 --- a/pypcode/sleigh/address.cc +++ b/pypcode/sleigh/address.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -666,6 +666,8 @@ uintb uintb_negate(uintb in,int4 size) uintb sign_extend(uintb in,int4 sizein,int4 sizeout) { + sizein = (sizein < sizeof(uintb)) ? sizein : sizeof(uintb); + sizeout = (sizeout < sizeof(uintb)) ? sizeout : sizeof(uintb); intb sval = in; sval <<= (sizeof(intb) - sizein) * 8; uintb res = (uintb)(sval >> (sizeout - sizein) * 8); diff --git a/pypcode/sleigh/address.hh b/pypcode/sleigh/address.hh index 5c42208b..45144daf 100644 --- a/pypcode/sleigh/address.hh +++ b/pypcode/sleigh/address.hh @@ -558,7 +558,7 @@ inline intb zero_extend(intb val,int4 bit) { int4 sa = sizeof(intb)*8 - (bit+1); - return (intb)((uintb)(val << sa) >> sa); + return (intb)(((uintb)val << sa) >> sa); } extern bool signbit_negative(uintb val,int4 size); ///< Return true if the sign-bit is set diff --git a/pypcode/sleigh/marshal.cc b/pypcode/sleigh/marshal.cc index 3610a7da..1c138774 100644 --- a/pypcode/sleigh/marshal.cc +++ b/pypcode/sleigh/marshal.cc @@ -1254,7 +1254,8 @@ AttributeId ATTRIB_WORDSIZE = AttributeId("wordsize",26); AttributeId ATTRIB_STORAGE = AttributeId("storage",149); AttributeId ATTRIB_STACKSPILL = AttributeId("stackspill",150); -AttributeId ATTRIB_UNKNOWN = AttributeId("XMLunknown",152); // Number serves as next open index +AttributeId ATTRIB_UNKNOWN = AttributeId("XMLunknown",159); // Number serves as next open index + ElementId ELEM_DATA = ElementId("data",1); ElementId ELEM_INPUT = ElementId("input",2); @@ -1267,6 +1268,6 @@ ElementId ELEM_VAL = ElementId("val",8); ElementId ELEM_VALUE = ElementId("value",9); ElementId ELEM_VOID = ElementId("void",10); -ElementId ELEM_UNKNOWN = ElementId("XMLunknown",288); // Number serves as next open index +ElementId ELEM_UNKNOWN = ElementId("XMLunknown",289); // Number serves as next open index } // End namespace ghidra diff --git a/pypcode/sleigh/opbehavior.cc b/pypcode/sleigh/opbehavior.cc index aebcfd91..ab23e94b 100644 --- a/pypcode/sleigh/opbehavior.cc +++ b/pypcode/sleigh/opbehavior.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -129,7 +129,20 @@ uintb OpBehavior::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) c string name(get_opname(opcode)); throw LowlevelError("Binary emulation unimplemented for "+name); } - + +/// \param sizeout is the size of the output in bytes +/// \param sizein is the size of the inputs in bytes +/// \param in1 is the first input value +/// \param in2 is the second input value +/// \param in3 is the third input value +/// \return the output value +uintb OpBehavior::evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const + +{ + string name(get_opname(opcode)); + throw LowlevelError("Ternary emulation unimplemented for "+name); +} + /// If the output value is known, recover the input value. /// \param sizeout is the size of the output in bytes /// \param out is the output value @@ -746,10 +759,26 @@ uintb OpBehaviorPiece::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb i uintb OpBehaviorSubpiece::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const { + if (in2 >= sizeof(uintb)) + return 0; uintb res = (in1>>(in2*8)) & calc_mask(sizeout); return res; } +uintb OpBehaviorPtradd::evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const + +{ + uintb res = (in1 + in2 * in3) & calc_mask(sizeout); + return res; +} + +uintb OpBehaviorPtrsub::evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const + +{ + uintb res = (in1 + in2) & calc_mask(sizeout); + return res; +} + uintb OpBehaviorPopcount::evaluateUnary(int4 sizeout,int4 sizein,uintb in1) const { diff --git a/pypcode/sleigh/opbehavior.hh b/pypcode/sleigh/opbehavior.hh index 2eb9752b..d1733c7a 100644 --- a/pypcode/sleigh/opbehavior.hh +++ b/pypcode/sleigh/opbehavior.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -66,7 +66,10 @@ public: /// \brief Emulate the binary op-code on input values virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const; - + + /// \brief Emulate the ternary op-code on input values + virtual uintb evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const; + /// \brief Reverse the binary op-code operation, recovering an input value virtual uintb recoverInputBinary(int4 slot,int4 sizeout,uintb out,int4 sizein,uintb in) const; @@ -506,6 +509,20 @@ public: virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const; }; +/// CPUI_PTRADD behavior +class OpBehaviorPtradd : public OpBehavior { +public: + OpBehaviorPtradd(void) : OpBehavior(CPUI_PTRADD,false) {} ///< Constructor + virtual uintb evaluateTernary(int4 sizeout,int4 sizein,uintb in1,uintb in2,uintb in3) const; +}; + +/// CPUI_PTRSUB behavior +class OpBehaviorPtrsub : public OpBehavior { +public: + OpBehaviorPtrsub(void) : OpBehavior(CPUI_PTRSUB,false) {} ///< Constructor + virtual uintb evaluateBinary(int4 sizeout,int4 sizein,uintb in1,uintb in2) const; +}; + /// CPUI_POPCOUNT behavior class OpBehaviorPopcount : public OpBehavior { public: diff --git a/pypcode/sleigh/pcodecompile.cc b/pypcode/sleigh/pcodecompile.cc index ca9d71ab..a67a3de8 100644 --- a/pypcode/sleigh/pcodecompile.cc +++ b/pypcode/sleigh/pcodecompile.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -583,9 +583,6 @@ VarnodeTpl *PcodeCompile::buildTruncatedVarnode(VarnodeTpl *basevn,uint4 bitoffs if ((bitoffset % 8) != 0) return (VarnodeTpl *)0; if ((numbits % 8) != 0) return (VarnodeTpl *)0; - if (basevn->getSpace().isUniqueSpace()) // Do we really want to prevent truncated uniques?? - return (VarnodeTpl *)0; - ConstTpl::const_type offset_type = basevn->getOffset().getType(); if ((offset_type != ConstTpl::real)&&(offset_type != ConstTpl::handle)) return (VarnodeTpl *)0; diff --git a/pypcode/sleigh/semantics.cc b/pypcode/sleigh/semantics.cc index cd9b9835..18e2ff8b 100644 --- a/pypcode/sleigh/semantics.cc +++ b/pypcode/sleigh/semantics.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -540,6 +540,18 @@ void VarnodeTpl::decode(Decoder &decoder) decoder.closeElement(el); } +bool VarnodeTpl::operator==(const VarnodeTpl &op2) const + +{ + return space==op2.space && offset==op2.offset && size==op2.size; +} + +bool VarnodeTpl::operator!=(const VarnodeTpl &op2) const + +{ + return !(*this == op2); +} + bool VarnodeTpl::operator<(const VarnodeTpl &op2) const { diff --git a/pypcode/sleigh/semantics.hh b/pypcode/sleigh/semantics.hh index e0b06995..b53b1879 100644 --- a/pypcode/sleigh/semantics.hh +++ b/pypcode/sleigh/semantics.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -91,6 +91,8 @@ public: bool isDynamic(const ParserWalker &walker) const; int4 transfer(const vector ¶ms); bool isZeroSize(void) const { return size.isZero(); } + bool operator==(const VarnodeTpl &op2) const; + bool operator!=(const VarnodeTpl &op2) const; bool operator<(const VarnodeTpl &op2) const; void setOffset(uintb constVal) { offset = ConstTpl(ConstTpl::real,constVal); } void setRelative(uintb constVal) { offset = ConstTpl(ConstTpl::j_relative,constVal); } diff --git a/pypcode/sleigh/sleigh.cc b/pypcode/sleigh/sleigh.cc index 66c1f49b..b72f116a 100644 --- a/pypcode/sleigh/sleigh.cc +++ b/pypcode/sleigh/sleigh.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -316,7 +316,7 @@ void SleighBuilder::buildEmpty(Constructor *ct,int4 secnum) void SleighBuilder::setUniqueOffset(const Address &addr) { - uniqueoffset = (addr.getOffset() & uniquemask)<<4; + uniqueoffset = (addr.getOffset() & uniquemask)<<8; } /// \brief Constructor @@ -337,7 +337,7 @@ SleighBuilder::SleighBuilder(ParserWalker *w,DisassemblyCache *dcache,PcodeCache const_space = cspc; uniq_space = uspc; uniquemask = umask; - uniqueoffset = (walker->getAddr().getOffset() & uniquemask)<<4; + uniqueoffset = (walker->getAddr().getOffset() & uniquemask)<<8; } void SleighBuilder::appendBuild(OpTpl *bld,int4 secnum) diff --git a/pypcode/sleigh/sleighbase.cc b/pypcode/sleigh/sleighbase.cc index 82cd8bcb..26805d64 100644 --- a/pypcode/sleigh/sleighbase.cc +++ b/pypcode/sleigh/sleighbase.cc @@ -17,7 +17,7 @@ namespace ghidra { -const uint4 SleighBase::MAX_UNIQUE_SIZE = 128; +const uint4 SleighBase::MAX_UNIQUE_SIZE = 256; int4 SourceFileIndexer::index(const string filename){ auto it = fileToIndex.find(filename); diff --git a/pypcode/sleigh/slgh_compile.cc b/pypcode/sleigh/slgh_compile.cc index 50d85e22..75bebffc 100644 --- a/pypcode/sleigh/slgh_compile.cc +++ b/pypcode/sleigh/slgh_compile.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -180,14 +180,82 @@ SubtableSymbol *WithBlock::getCurrentSubtable(const list &stack) return (SubtableSymbol *)0; } +void ConsistencyChecker::OptimizeRecord::copyFromExcludingSize(ConsistencyChecker::OptimizeRecord &that) + +{ + this->writeop = that.writeop; + this->readop = that.readop; + this->inslot = that.inslot; + this->writecount = that.writecount; + this->readcount = that.readcount; + this->writesection = that.writesection; + this->readsection = that.readsection; + this->opttype = that.opttype; +} + +void ConsistencyChecker::OptimizeRecord::update(int4 opIdx, int4 slotIdx, int4 secNum) + +{ + if (slotIdx >= 0) { + updateRead(opIdx, slotIdx, secNum); + } + else { + updateWrite(opIdx, secNum); + } +} + +void ConsistencyChecker::OptimizeRecord::updateRead(int4 i, int4 inslot, int4 secNum) + +{ + this->readop = i; + this->readcount++; + this->inslot = inslot; + this->readsection = secNum; +} + +void ConsistencyChecker::OptimizeRecord::updateWrite(int4 i, int4 secNum) + +{ + this->writeop = i; + this->writecount++; + this->writesection = secNum; +} + +void ConsistencyChecker::OptimizeRecord::updateExport() + +{ + this->writeop = 0; + this->readop = 0; + this->writecount = 2; + this->readcount = 2; + this->readsection = -2; + this->writesection = -2; +} + +void ConsistencyChecker::OptimizeRecord::updateCombine(ConsistencyChecker::OptimizeRecord &that) + +{ + if (that.writecount != 0) { + this->writeop = that.writeop; + this->writesection = that.writesection; + } + if (that.readcount != 0) { + this->readop = that.readop; + this->inslot = that.inslot; + this->readsection = that.readsection; + } + this->writecount += that.writecount; + this->readcount += that.readcount; + // opttype is not relevant here +} + /// \brief Construct the consistency checker and optimizer /// /// \param sleigh is the parsed SLEIGH spec /// \param rt is the root subtable of the SLEIGH spec /// \param un is \b true to request "Unnecessary extension" warnings /// \param warndead is \b true to request warnings for written but not read temporaries -/// \param warnlargetemp is \b true to request warnings for temporaries that are too large -ConsistencyChecker::ConsistencyChecker(SleighCompile *sleigh,SubtableSymbol *rt,bool un,bool warndead, bool warnlargetemp) +ConsistencyChecker::ConsistencyChecker(SleighCompile *sleigh,SubtableSymbol *rt,bool un,bool warndead) { compiler = sleigh; @@ -195,10 +263,8 @@ ConsistencyChecker::ConsistencyChecker(SleighCompile *sleigh,SubtableSymbol *rt, unnecessarypcode = 0; readnowrite = 0; writenoread = 0; - largetemp = 0; ///::iterator ConsistencyChecker::UniqueState::lesserIter(uintb offset) + +{ + if (recs.begin() == recs.end()) { + return recs.end(); + } + map::iterator iter; + iter = recs.lower_bound(offset); + if (iter == recs.begin()) { + return recs.end(); + } + return std::prev(iter); +} + +ConsistencyChecker::OptimizeRecord ConsistencyChecker::UniqueState::coalesce(vector &records) + +{ + uintb minOff = -1; + uintb maxOff = -1; + vector::iterator iter; + + for (iter = records.begin(); iter != records.end(); ++iter) { + if (minOff == -1 || (*iter)->offset < minOff) { + minOff = (*iter)->offset; + } + if (maxOff == -1 || (*iter)->offset + (*iter)->size > maxOff) { + maxOff = (*iter)->offset + (*iter)->size; + } + } + + OptimizeRecord result(minOff, maxOff - minOff); + + for (iter = records.begin(); iter != records.end(); ++iter) { + result.updateCombine(**iter); + } + + return result; +} + +void ConsistencyChecker::UniqueState::set(uintb offset, int4 size, OptimizeRecord &rec) + +{ + vector records; + getDefinitions(records, offset, size); + records.push_back(&rec); + OptimizeRecord coalesced = coalesce(records); + recs.erase(recs.lower_bound(coalesced.offset), recs.lower_bound(coalesced.offset+coalesced.size)); + recs.insert(pair(coalesced.offset, coalesced)); +} + +void ConsistencyChecker::UniqueState::getDefinitions(vector &result, uintb offset, int4 size) + +{ + if (size == 0) { + size = 1; + } + map::iterator iter; + iter = lesserIter(offset); + uintb cursor = offset; + if (iter != recs.end() && endOf(iter) > offset) { + OptimizeRecord &preRec = iter->second; + cursor = endOf(iter); + result.push_back(&preRec); + } + uintb end = offset + size; + iter = recs.lower_bound(offset); + while (iter != recs.end() && iter->first < end) { + if (iter->first > cursor) { + // The iterator becomes invalid with this insertion, so take the new one. + iter = recs.insert(pair(cursor,OptimizeRecord(cursor, iter->first - cursor))).first; + result.push_back(&iter->second); + iter++; // Put the (now valid) iterator back to where it was. + } + // No need to truncate, as we're just counting a read + result.push_back(&iter->second); + cursor = endOf(iter); + iter++; + } + if (end > cursor) { + iter = recs.insert(pair(cursor,OptimizeRecord(cursor, end - cursor))).first; + result.push_back(&iter->second); + } +} + /// \brief Test whether two given Varnodes intersect /// /// This test must be conservative. If it can't explicitly prove that the @@ -1222,30 +1372,31 @@ bool ConsistencyChecker::readWriteInterference(const VarnodeTpl *vn,const OpTpl /// If the Varnode is in the \e unique space, an OptimizationRecord for it is looked /// up based on its offset. Information about how a p-code operator uses the Varnode /// is accumulated in the record. -/// \param recs is collection of OptimizationRecords associated with temporary Varnodes +/// \param state is collection of OptimizationRecords associated with temporary Varnodes /// \param vn is the given Varnode to check (which may or may not be temporary) /// \param i is the index of the operator using the Varnode (within its p-code section) /// \param inslot is the \e slot index of the Varnode within its operator /// \param secnum is the section number containing the operator -void ConsistencyChecker::examineVn(map &recs, +void ConsistencyChecker::examineVn(UniqueState &state, const VarnodeTpl *vn,uint4 i,int4 inslot,int4 secnum) { if (vn == (const VarnodeTpl *)0) return; if (!vn->getSpace().isUniqueSpace()) return; if (vn->getOffset().getType() != ConstTpl::real) return; - map::iterator iter; - iter = recs.insert( pair(vn->getOffset().getReal(),OptimizeRecord())).first; - if (inslot>=0) { - (*iter).second.readop = i; - (*iter).second.readcount += 1; - (*iter).second.inslot = inslot; - (*iter).second.readsection = secnum; + uintb offset = vn->getOffset().getReal(); + int4 size = vn->getSize().getReal(); + if (inslot >= 0) { + vector defs; + state.getDefinitions(defs,offset,size); + for (vector::iterator iter=defs.begin();iter!=defs.end();++iter) { + (*iter)->updateRead(i,inslot,secnum); + } } else { - (*iter).second.writeop = i; - (*iter).second.writecount += 1; - (*iter).second.writesection = secnum; + OptimizeRecord rec(offset,size); + rec.updateWrite(i,secnum); + state.set(offset,size,rec); } } @@ -1254,9 +1405,9 @@ void ConsistencyChecker::examineVn(map &recs, /// For each temporary Varnode, count how many times it is read from or written to /// in the given section of p-code operators. /// \param ct is the given Constructor -/// \param recs is the (initially empty) collection of count records +/// \param state is the (initially empty) collection of count records /// \param secnum is the given p-code section number -void ConsistencyChecker::optimizeGather1(Constructor *ct,map &recs,int4 secnum) const +void ConsistencyChecker::optimizeGather1(Constructor *ct,UniqueState &state,int4 secnum) const { ConstructTpl *tpl; @@ -1271,10 +1422,10 @@ void ConsistencyChecker::optimizeGather1(Constructor *ct,mapnumInput();++j) { const VarnodeTpl *vnin = op->getIn(j); - examineVn(recs,vnin,i,j,secnum); + examineVn(state,vnin,i,j,secnum); } const VarnodeTpl *vn = op->getOut(); - examineVn(recs,vn,i,-1,secnum); + examineVn(state,vn,i,-1,secnum); } } @@ -1284,9 +1435,9 @@ void ConsistencyChecker::optimizeGather1(Constructor *ct,map &recs,int4 secnum) const +void ConsistencyChecker::optimizeGather2(Constructor *ct,UniqueState &state,int4 secnum) const { ConstructTpl *tpl; @@ -1300,29 +1451,29 @@ void ConsistencyChecker::optimizeGather2(Constructor *ct,mapgetPtrSpace().isUniqueSpace()) { if (hand->getPtrOffset().getType() == ConstTpl::real) { - pair::iterator,bool> res; uintb offset = hand->getPtrOffset().getReal(); - res = recs.insert( pair(offset,OptimizeRecord())); - (*res.first).second.writeop = 0; - (*res.first).second.readop = 0; - (*res.first).second.writecount = 2; - (*res.first).second.readcount = 2; - (*res.first).second.readsection = -2; - (*res.first).second.writesection = -2; + int4 size = hand->getPtrSize().getReal(); + vector defs; + state.getDefinitions(defs,offset,size); + for (vector::iterator iter=defs.begin();iter!=defs.end();++iter) { + (*iter)->updateExport(); + // NOTE: Could this just be updateRead? + // Technically, an exported handle could be written by the parent.... + } } } if (hand->getSpace().isUniqueSpace()) { if ((hand->getPtrSpace().getType() == ConstTpl::real)&& (hand->getPtrOffset().getType() == ConstTpl::real)) { - pair::iterator,bool> res; uintb offset = hand->getPtrOffset().getReal(); - res = recs.insert( pair(offset,OptimizeRecord())); - (*res.first).second.writeop = 0; - (*res.first).second.readop = 0; - (*res.first).second.writecount = 2; - (*res.first).second.readcount = 2; - (*res.first).second.readsection = -2; - (*res.first).second.writesection = -2; + int4 size = hand->getPtrSize().getReal(); + vector defs; + state.getDefinitions(defs,offset,size); + for (vector::iterator iter=defs.begin();iter!=defs.end();++iter) { + (*iter)->updateExport(); + // NOTE: Could this just be updateRead? + // Technically, an exported handle could be written by the parent.... + } } } } @@ -1336,14 +1487,14 @@ void ConsistencyChecker::optimizeGather2(Constructor *ct,map &recs) const + const UniqueState &state) const { map::const_iterator iter; - iter = recs.begin(); - while(iter != recs.end()) { + iter = state.begin(); + while(iter!=state.end()) { const OptimizeRecord &currec( (*iter).second ); ++iter; if ((currec.writecount==1)&&(currec.readcount==1)&&(currec.readsection==currec.writesection)) { @@ -1354,13 +1505,27 @@ const ConsistencyChecker::OptimizeRecord *ConsistencyChecker::findValidRule(Cons else tpl = ct->getNamedTempl(currec.readsection); const vector &ops( tpl->getOpvec() ); - const OpTpl *op = ops[ currec.readop ]; + const OpTpl *writeop = ops[ currec.writeop ]; + const OpTpl *readop = ops[ currec.readop ]; if (currec.writeop >= currec.readop) // Read must come after write throw SleighError("Read of temporary before write"); - if (op->getOpcode() == CPUI_COPY) { + + VarnodeTpl *writevn = writeop->getOut(); + VarnodeTpl *readvn = readop->getIn(currec.inslot); + // Because the record can change size and position, we have to check if the varnode + // "connecting" the write and read ops is actually the same varnode. If not, then we can't + // optimize it out. + // There may be an opportunity here to re-write the size/offset when either the write or read + // op is a COPY, but I'll leave that for later discussion. + // Actually, maybe not. If the truncate would be of a handle, we can't. + if (*writevn != *readvn) { + continue; + } + + if (readop->getOpcode() == CPUI_COPY) { bool saverecord = true; currec.opttype = 0; // Read op is a COPY - const VarnodeTpl *vn = op->getOut(); + const VarnodeTpl *vn = readop->getOut(); for(int4 i=currec.writeop+1;igetOpcode() == CPUI_COPY) { + if (writeop->getOpcode() == CPUI_COPY) { bool saverecord = true; currec.opttype = 1; // Write op is a COPY - const VarnodeTpl *vn = op->getIn(0); + const VarnodeTpl *vn = writeop->getIn(0); for(int4 i=currec.writeop+1;i &recs) +/// \param state is the collection of records associated with each temporary Varnode +void ConsistencyChecker::checkUnusedTemps(Constructor *ct,const UniqueState &state) { map::const_iterator iter; - iter = recs.begin(); - while(iter != recs.end()) { + iter = state.begin(); + while(iter != state.end()) { const OptimizeRecord &currec( (*iter).second ); if (currec.readcount == 0) { if (printdeadwarning) @@ -1465,12 +1629,9 @@ void ConsistencyChecker::checkLargeTemporaries(Constructor *ct,ConstructTpl *ctp vector ops = ctpl->getOpvec(); for(vector::iterator iter = ops.begin();iter != ops.end();++iter) { if (hasLargeTemporary(*iter)) { - if (printlargetempwarning) { - compiler->reportWarning( - compiler->getLocation(ct), - "Constructor uses temporary varnode larger than " + to_string(SleighBase::MAX_UNIQUE_SIZE) + " bytes."); - } - largetemp++; + compiler->reportError( + compiler->getLocation(ct), + "Constructor uses temporary varnode larger than " + to_string(SleighBase::MAX_UNIQUE_SIZE) + " bytes."); return; } } @@ -1485,19 +1646,19 @@ void ConsistencyChecker::optimize(Constructor *ct) { const OptimizeRecord *currec; - map recs; + UniqueState state; int4 numsections = ct->getNumSections(); do { - recs.clear(); + state.clear(); for(int4 i=-1;i 0)) { - ostringstream msg; - msg << dec << checker.getNumLargeTemporaries(); - msg << " constructors contain temporaries larger than "; - msg << SleighBase::MAX_UNIQUE_SIZE << " bytes"; - reportWarning(msg.str()); - reportWarning("Use -o switch to list each individually."); - } } /// \brief Search for offset matches between a previous set and the given current set @@ -3171,6 +3330,18 @@ vector *SleighCompile::createCrossBuild(VarnodeTpl *addr,SectionSymbol return res; } +/// \brief Prepare for a new section of p-code templates +/// +/// Create the ConstructTpl to hold the templates and reset counters. +/// \return the new ConstructTpl +ConstructTpl *SleighCompile::enterSection(void) + +{ + ConstructTpl *tpl = new ConstructTpl(); + pcode.resetLabelCount(); // Macros have their own labels + return tpl; +} + /// \brief Create a new Constructor under the given subtable /// /// Create the object and initialize parsing for the new definition @@ -3374,73 +3545,77 @@ bool SleighCompile::forceExportSize(ConstructTpl *ct) return true; } -/// \brief If the given Varnode is in the \e unique space, shift its offset up by \b sa bits +/// \brief Insert a region of zero bits into an address offset +/// +/// \param addr is the address offset +/// \return the modified offset +uintb SleighCompile::insertCrossBuildRegion(uintb addr) + +{ + uintb upperbits = (addr >> UNIQUE_CROSSBUILD_POSITION) << (UNIQUE_CROSSBUILD_POSITION + UNIQUE_CROSSBUILD_NUMBITS); + uintb lowerbits = (addr << (8*sizeof(uintb) - UNIQUE_CROSSBUILD_POSITION)) >> (8*sizeof(uintb) - UNIQUE_CROSSBUILD_POSITION); + return upperbits | lowerbits; +} + +/// \brief If the given Varnode is in the \e unique space, insert a region of zero bits /// /// \param vn is the given Varnode -/// \param sa is the number of bits to shift by -void SleighCompile::shiftUniqueVn(VarnodeTpl *vn,int4 sa) +void SleighCompile::shiftUniqueVn(VarnodeTpl *vn) { if (vn->getSpace().isUniqueSpace() && (vn->getOffset().getType() == ConstTpl::real)) { - uintb val = vn->getOffset().getReal(); - val <<= sa; + uintb val = insertCrossBuildRegion(vn->getOffset().getReal()); vn->setOffset(val); } } -/// \brief Shift the offset up by \b sa bits for any Varnode used by the given op in the \e unique space +/// \brief Insert a region of zero bits for any Varnode used by the given op in the \e unique space /// /// \param op is the given op -/// \param sa is the number of bits to shift by -void SleighCompile::shiftUniqueOp(OpTpl *op,int4 sa) +void SleighCompile::shiftUniqueOp(OpTpl *op) { VarnodeTpl *outvn = op->getOut(); if (outvn != (VarnodeTpl *)0) - shiftUniqueVn(outvn,sa); + shiftUniqueVn(outvn); for(int4 i=0;inumInput();++i) - shiftUniqueVn(op->getIn(i),sa); + shiftUniqueVn(op->getIn(i)); } -/// \brief Shift the offset up for both \e dynamic or \e static Varnode aspects in the \e unique space +/// \brief Insert a region of zero bits for both \e dynamic or \e static Varnode aspects in the \e unique space /// /// \param hand is a handle template whose aspects should be modified -/// \param sa is the number of bits to shift by -void SleighCompile::shiftUniqueHandle(HandleTpl *hand,int4 sa) +void SleighCompile::shiftUniqueHandle(HandleTpl *hand) { if (hand->getSpace().isUniqueSpace() && (hand->getPtrSpace().getType() == ConstTpl::real) && (hand->getPtrOffset().getType() == ConstTpl::real)) { - uintb val = hand->getPtrOffset().getReal(); - val <<= sa; + uintb val = insertCrossBuildRegion(hand->getPtrOffset().getReal()); hand->setPtrOffset(val); } else if (hand->getPtrSpace().isUniqueSpace() && (hand->getPtrOffset().getType() == ConstTpl::real)) { - uintb val = hand->getPtrOffset().getReal(); - val <<= sa; + uintb val = insertCrossBuildRegion(hand->getPtrOffset().getReal()); hand->setPtrOffset(val); } if (hand->getTempSpace().isUniqueSpace() && (hand->getTempOffset().getType() == ConstTpl::real)) { - uintb val = hand->getTempOffset().getReal(); - val <<= sa; + uintb val = insertCrossBuildRegion(hand->getTempOffset().getReal()); hand->setTempOffset(val); } } -/// \brief Shift the offset up for any Varnode in the \e unique space for all p-code in the given section +/// \brief Insert a region of zero bits for any Varnode in the \e unique space for all p-code in the given section /// /// \param tpl is the given p-code section -/// \param sa is the number of bits to shift by -void SleighCompile::shiftUniqueConstruct(ConstructTpl *tpl,int4 sa) +void SleighCompile::shiftUniqueConstruct(ConstructTpl *tpl) { HandleTpl *result = tpl->getResult(); if (result != (HandleTpl *)0) - shiftUniqueHandle(result,sa); + shiftUniqueHandle(result); const vector &vec( tpl->getOpvec() ); for(int4 i=0;igetConstructor(j); ConstructTpl *tpl = ct->getTempl(); if (tpl != (ConstructTpl *)0) - shiftUniqueConstruct(tpl,sa); + shiftUniqueConstruct(tpl); for(int4 k=0;kgetNamedTempl(k); if (namedtpl != (ConstructTpl *)0) - shiftUniqueConstruct(namedtpl,sa); + shiftUniqueConstruct(namedtpl); } } i+=1; @@ -3474,7 +3648,8 @@ void SleighCompile::checkUniqueAllocation(void) sym = tables[i]; } uint4 ubase = getUniqueBase(); // We have to adjust the unique base - ubase <<= sa; + ubase += 1 << UNIQUE_CROSSBUILD_POSITION; + ubase <<= UNIQUE_CROSSBUILD_NUMBITS; setUniqueBase(ubase); } @@ -3704,13 +3879,12 @@ static void findSlaSpecs(vector &res, const string &dir, const string &s /// \param allNopWarning is \b true for individual warnings about NOP constructors /// \param deadTempWarning is \b true for individual warnings about dead temporary varnodes /// \param enforceLocalKeyWord is \b true to force all local variable definitions to use the \b local keyword -/// \param largeTemporaryWarning is \b true for individual warnings about temporary varnodes that are too large /// \param caseSensitiveRegisterNames is \b true if register names are allowed to be case sensitive /// \param debugOutput is \b true if the output file is written using the debug (XML) form of the .sla format void SleighCompile::setAllOptions(const map &defines, bool unnecessaryPcodeWarning, bool lenientConflict, bool allCollisionWarning, bool allNopWarning,bool deadTempWarning,bool enforceLocalKeyWord, - bool largeTemporaryWarning, bool caseSensitiveRegisterNames,bool debugOutput) + bool caseSensitiveRegisterNames,bool debugOutput) { map::const_iterator iter = defines.begin(); for (iter = defines.begin(); iter != defines.end(); iter++) { @@ -3722,7 +3896,6 @@ void SleighCompile::setAllOptions(const map &defines, bool unnece setAllNopWarning( allNopWarning ); setDeadTempWarning(deadTempWarning); setEnforceLocalKeyWord(enforceLocalKeyWord); - setLargeTemporaryWarning(largeTemporaryWarning); setInsensitiveDuplicateError(!caseSensitiveRegisterNames); setDebugOutput(debugOutput); } @@ -3757,7 +3930,6 @@ int main(int argc,char **argv) cerr << " -t print warnings for dead temporaries" << endl; cerr << " -e enforce use of 'local' keyword for temporaries" << endl; cerr << " -c print warnings for all constructors with colliding operands" << endl; - cerr << " -o print warnings for temporaries which are too large" << endl; cerr << " -s treat register names as case sensitive" << endl; cerr << " -DNAME=VALUE defines a preprocessor macro NAME with value VALUE" << endl; exit(2); @@ -3772,7 +3944,6 @@ int main(int argc,char **argv) bool allNopWarning = false; bool deadTempWarning = false; bool enforceLocalKeyWord = false; - bool largeTemporaryWarning = false; bool caseSensitiveRegisterNames = false; bool debugOutput = false; @@ -3806,8 +3977,6 @@ int main(int argc,char **argv) deadTempWarning = true; else if (argv[i][1] == 'e') enforceLocalKeyWord = true; - else if (argv[i][1] == 'o') - largeTemporaryWarning = true; else if (argv[i][1] == 's') caseSensitiveRegisterNames = true; else if (argv[i][1] == 'y') @@ -3843,8 +4012,7 @@ int main(int argc,char **argv) sla.replace(slaspec.length() - slaspecExtLen, slaspecExtLen, SLAEXT); SleighCompile compiler; compiler.setAllOptions(defines, unnecessaryPcodeWarning, lenientConflict, allCollisionWarning, allNopWarning, - deadTempWarning, enforceLocalKeyWord,largeTemporaryWarning, caseSensitiveRegisterNames, - debugOutput); + deadTempWarning, enforceLocalKeyWord, caseSensitiveRegisterNames, debugOutput); retval = compiler.run_compilation(slaspec,sla); if (retval != 0) { return retval; // stop on first error @@ -3880,8 +4048,7 @@ int main(int argc,char **argv) SleighCompile compiler; compiler.setAllOptions(defines, unnecessaryPcodeWarning, lenientConflict, allCollisionWarning, allNopWarning, - deadTempWarning, enforceLocalKeyWord,largeTemporaryWarning,caseSensitiveRegisterNames, - debugOutput); + deadTempWarning, enforceLocalKeyWord,caseSensitiveRegisterNames,debugOutput); if (i < argc - 1) { string fileoutExamine(argv[i+1]); diff --git a/pypcode/sleigh/slgh_compile.hh b/pypcode/sleigh/slgh_compile.hh index 88fe7df7..a193c7db 100644 --- a/pypcode/sleigh/slgh_compile.hh +++ b/pypcode/sleigh/slgh_compile.hh @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -23,12 +23,14 @@ #include "filemanage.hh" #include #include +#include namespace ghidra { using std::cout; using std::cerr; using std::out_of_range; +using std::string; /// \brief A helper class to associate a \e named Constructor section with its symbol scope /// @@ -137,34 +139,57 @@ class SleighCompile; /// This class searches for unnecessary truncations and extensions, temporary varnodes that are either dead, /// read before written, or that exceed the standard allocation size. class ConsistencyChecker { - +public: /// \brief Description of how a temporary register is being used within a Constructor /// /// This counts reads and writes of the register. If the register is read only once, the /// particular p-code op and input slot reading it is recorded. If the register is written /// only once, the particular p-code op writing it is recorded. struct OptimizeRecord { - int4 writeop; ///< Index of the (last) p-code op writing to register (or -1) - int4 readop; ///< Index of the (last) p-code op reading the register (or -1) - int4 inslot; ///< Input slot of p-code op reading the register (or -1) - int4 writecount; ///< Number of times the register is written - int4 readcount; ///< Number of times the register is read - int4 writesection; ///< Section containing (last) p-code op writing to the register (or -2) - int4 readsection; ///< Section containing (last) p-code op reading the register (or -2) - mutable int4 opttype; ///< 0 = register read by a COPY, 1 = register written by a COPY (-1 otherwise) + uintb offset; ///< Offset of the varnode address + int4 size; ///< Size in bytes of the varnode or piece (immutable) + int4 writeop; ///< Index of the (last) p-code op writing to register (or -1) + int4 readop; ///< Index of the (last) p-code op reading the register (or -1) + int4 inslot; ///< Input slot of p-code op reading the register (or -1) + int4 writecount; ///< Number of times the register is written + int4 readcount; ///< Number of times the register is read + int4 writesection; ///< Section containing (last) p-code op writing to the register (or -2) + int4 readsection; ///< Section containing (last) p-code op reading the register (or -2) + mutable int4 opttype; ///< 0 = register read by a COPY, 1 = register written by a COPY (-1 otherwise) /// \brief Construct a record, initializing counts - OptimizeRecord(void) { - writeop = -1; readop = -1; inslot=-1; writecount=0; readcount=0; writesection=-2; readsection=-2; opttype=-1; } + OptimizeRecord(uintb offset, int4 size) { + this->offset = offset; + this->size = size; + writeop = -1; readop = -1; inslot=-1; writecount=0; readcount=0; writesection=-2; readsection=-2; opttype=-1; + } + void copyFromExcludingSize(OptimizeRecord &that); + void update(int4 opIdx, int4 slotIdx, int4 secNum); + void updateRead(int4 i, int4 inslot, int4 secNum); + void updateWrite(int4 i, int4 secNum); + void updateExport(); + void updateCombine(OptimizeRecord &that); + }; +private: + class UniqueState { + map recs; + static uintb endOf(map::iterator &iter) { return iter->first + iter->second.size; } + OptimizeRecord coalesce(vector &records); + map::iterator lesserIter(uintb offset); + public: + void clear(void) { recs.clear(); } + void set(uintb offset, int4 size, OptimizeRecord &rec); + void getDefinitions(vector &result, uintb offset, int4 size); + map::const_iterator begin(void) const { return recs.begin(); } + map::const_iterator end(void) const { return recs.end(); } }; + SleighCompile *compiler; ///< Parsed form of the SLEIGH file being examined int4 unnecessarypcode; ///< Count of unnecessary extension/truncation operations int4 readnowrite; ///< Count of temporary registers that are read but not written int4 writenoread; ///< Count of temporary registers that are written but not read - int4 largetemp; ///< Count of temporary registers that are too large bool printextwarning; ///< Set to \b true if warning emitted for each unnecessary truncation/extension bool printdeadwarning; ///< Set to \b true if warning emitted for each written but not read temporary - bool printlargetempwarning; ///< Set to \b true if warning emitted for each too large temporary SubtableSymbol *root_symbol; ///< The root symbol table for the parsed SLEIGH file vector postorder; ///< Subtables sorted into \e post order (dependent tables listed earlier) map sizemap; ///< Sizes associated with table \e exports @@ -185,18 +210,18 @@ class ConsistencyChecker { void setPostOrder(SubtableSymbol *root); // Optimization routines - static void examineVn(map &recs,const VarnodeTpl *vn,uint4 i,int4 inslot,int4 secnum); + static void examineVn(UniqueState &state,const VarnodeTpl *vn,uint4 i,int4 inslot,int4 secnum); static bool possibleIntersection(const VarnodeTpl *vn1,const VarnodeTpl *vn2); bool readWriteInterference(const VarnodeTpl *vn,const OpTpl *op,bool checkread) const; - void optimizeGather1(Constructor *ct,map &recs,int4 secnum) const; - void optimizeGather2(Constructor *ct,map &recs,int4 secnum) const; - const OptimizeRecord *findValidRule(Constructor *ct,const map &recs) const; + void optimizeGather1(Constructor *ct,UniqueState &state,int4 secnum) const; + void optimizeGather2(Constructor *ct,UniqueState &state,int4 secnum) const; + const OptimizeRecord *findValidRule(Constructor *ct,const UniqueState &state) const; void applyOptimization(Constructor *ct,const OptimizeRecord &rec); - void checkUnusedTemps(Constructor *ct,const map &recs); + void checkUnusedTemps(Constructor *ct,const UniqueState &state); void checkLargeTemporaries(Constructor *ct,ConstructTpl *ctpl); void optimize(Constructor *ct); public: - ConsistencyChecker(SleighCompile *sleigh, SubtableSymbol *rt,bool unnecessary,bool warndead, bool warnlargetemp); + ConsistencyChecker(SleighCompile *sleigh, SubtableSymbol *rt,bool unnecessary,bool warndead); bool testSizeRestrictions(void); ///< Test size consistency of all p-code bool testTruncations(void); ///< Test truncation validity of all p-code void testLargeTemporary(void); ///< Test for temporary Varnodes that are too large @@ -204,7 +229,6 @@ public: int4 getNumUnnecessaryPcode(void) const { return unnecessarypcode; } ///< Return the number of unnecessary extensions and truncations int4 getNumReadNoWrite(void) const { return readnowrite; } ///< Return the number of temporaries read but not written int4 getNumWriteNoRead(void) const { return writenoread; } ///< Return the number of temporaries written but not read - int4 getNumLargeTemporaries(void) const {return largetemp;} ///< Return the number of \e too large temporaries }; /// \brief Helper function holding properties of a \e context field prior to calculating the context layout @@ -274,6 +298,8 @@ public: /// various set*() methods prior to calling run_compilation. class SleighCompile : public SleighBase { friend class SleighPcode; + static const int4 UNIQUE_CROSSBUILD_POSITION = 8; + static const int4 UNIQUE_CROSSBUILD_NUMBITS = 8; public: SleighPcode pcode; ///< The p-code parsing (sub)engine private: @@ -296,7 +322,6 @@ private: bool warnunnecessarypcode; ///< \b true if we warn of unnecessary ZEXT or SEXT bool warndeadtemps; ///< \b true if we warn of temporaries that are written but not read bool lenientconflicterrors; ///< \b true if we ignore most pattern conflict errors - bool largetemporarywarning; ///< \b true if we warn about temporaries larger than SleighBase::MAX_UNIQUE_SIZE bool warnalllocalcollisions; ///< \b true if local export collisions generate individual warnings bool warnallnops; ///< \b true if pcode NOPs generate individual warnings bool failinsensitivedups; ///< \b true if case insensitive register duplicates cause error @@ -324,10 +349,11 @@ private: bool finalizeSections(Constructor *big,SectionVector *vec); ///< Do final checks, expansions, and linking for p-code sections static VarnodeTpl *findSize(const ConstTpl &offset,const ConstructTpl *ct); static bool forceExportSize(ConstructTpl *ct); - static void shiftUniqueVn(VarnodeTpl *vn,int4 sa); - static void shiftUniqueOp(OpTpl *op,int4 sa); - static void shiftUniqueHandle(HandleTpl *hand,int4 sa); - static void shiftUniqueConstruct(ConstructTpl *tpl,int4 sa); + static uintb insertCrossBuildRegion(uintb addr); + static void shiftUniqueVn(VarnodeTpl *vn); + static void shiftUniqueOp(OpTpl *op); + static void shiftUniqueHandle(HandleTpl *hand); + static void shiftUniqueConstruct(ConstructTpl *tpl); static string formatStatusMessage(const Location* loc, const string &msg); void checkUniqueAllocation(void); ///< Modify temporary Varnode offsets to support \b crossbuilds void process(void); ///< Do all post processing on the parsed data structures @@ -358,11 +384,6 @@ public: /// \param val is \b true if the \b local keyword must always be used. The default is \b false. void setEnforceLocalKeyWord(bool val) { pcode.setEnforceLocalKey(val); } - /// \brief Set whether too large temporary registers generate warnings individually - /// - /// \param val is \b true if warnings are generated individually. The default is \b false. - void setLargeTemporaryWarning (bool val) {largetemporarywarning = val;} - /// \brief Set whether indistinguishable Constructor patterns generate fatal errors /// /// \param val is \b true if no error is generated. The default is \b true. @@ -436,6 +457,7 @@ public: SectionVector *nextNamedSection(SectionVector *vec,ConstructTpl *section,SectionSymbol *sym); SectionVector *finalNamedSection(SectionVector *vec,ConstructTpl *section); vector *createCrossBuild(VarnodeTpl *addr,SectionSymbol *sym); + ConstructTpl *enterSection(void); Constructor *createConstructor(SubtableSymbol *sym); bool isInRoot(Constructor *ct) const { return (root == ct->getParent()); } ///< Is the Constructor in the root table? void resetConstructors(void); @@ -454,10 +476,12 @@ public: void setAllOptions(const map &defines, bool unnecessaryPcodeWarning, bool lenientConflict, bool allCollisionWarning, bool allNopWarning,bool deadTempWarning,bool enforceLocalKeyWord, - bool largeTemporaryWarning, bool caseSensitiveRegisterNames,bool debugOutput); + bool caseSensitiveRegisterNames,bool debugOutput); int4 run_compilation(const string &filein,const string &fileout); }; +ostream& operator<<(ostream &os, const ConsistencyChecker::OptimizeRecord &rec); + extern SleighCompile *slgh; ///< A global reference to the SLEIGH compiler accessible to the parse functions extern int yydebug; ///< Debug state for the SLEIGH parse functions diff --git a/pypcode/sleigh/slghparse.cc b/pypcode/sleigh/slghparse.cc index ec1f76a0..741525a3 100644 --- a/pypcode/sleigh/slghparse.cc +++ b/pypcode/sleigh/slghparse.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -2856,7 +2856,7 @@ yyparse (void) break; case 145: - { (yyval.sem) = new ConstructTpl(); } + { (yyval.sem) = slgh->enterSection(); } break; case 146: diff --git a/pypcode/sleigh/slghparse.y b/pypcode/sleigh/slghparse.y index fd7f293e..cddc09f5 100644 --- a/pypcode/sleigh/slghparse.y +++ b/pypcode/sleigh/slghparse.y @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -350,7 +350,7 @@ rtl: rtlmid { $$ = $1; if ($$->getOpvec().empty() && ($$->getResult() == (Handle | rtlmid EXPORT_KEY STRING { string errmsg="Unknown export varnode: "+*$3; delete $3; slgh->reportError(errmsg); YYERROR; } | rtlmid EXPORT_KEY sizedstar STRING { string errmsg="Unknown pointer varnode: "+*$4; delete $3; delete $4; slgh->reportError(errmsg); YYERROR; } ; -rtlmid: /* EMPTY */ { $$ = new ConstructTpl(); } +rtlmid: /* EMPTY */ { $$ = slgh->enterSection(); } | rtlmid statement { $$ = $1; if (!$$->addOpList(*$2)) { delete $2; slgh->reportError("Multiple delayslot declarations"); YYERROR; } delete $2; } | rtlmid LOCAL_KEY STRING ';' { $$ = $1; slgh->pcode.newLocalDefinition($3); } | rtlmid LOCAL_KEY STRING ':' INTEGER ';' { $$ = $1; slgh->pcode.newLocalDefinition($3,*$5); delete $5; } diff --git a/pypcode/sleigh/slghsymbol.cc b/pypcode/sleigh/slghsymbol.cc index b35dd6ec..e62c4708 100644 --- a/pypcode/sleigh/slghsymbol.cc +++ b/pypcode/sleigh/slghsymbol.cc @@ -4,9 +4,9 @@ * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at - * + * * http://www.apache.org/licenses/LICENSE-2.0 - * + * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. @@ -2415,7 +2415,7 @@ void ContextOp::decode(Decoder &decoder,SleighBase *trans) num = decoder.readSignedInteger(sla::ATTRIB_I); shift = decoder.readSignedInteger(sla::ATTRIB_SHIFT); mask = decoder.readUnsignedInteger(sla::ATTRIB_MASK); - patexp = (PatternValue *)PatternExpression::decodeExpression(decoder,trans); + patexp = PatternExpression::decodeExpression(decoder,trans); patexp->layClaim(); decoder.closeElement(el); } diff --git a/scripts/sleigh_download.sh b/scripts/sleigh_download.sh index d95f9252..ef936847 100755 --- a/scripts/sleigh_download.sh +++ b/scripts/sleigh_download.sh @@ -2,7 +2,7 @@ set -e set -x -TAG=11.4.2 +TAG=12.0.1 GHIDRA_SRC_DIR=ghidra_src_${TAG} git clone --depth=1 -b Ghidra_${TAG}_build https://github.com/NationalSecurityAgency/ghidra.git ${GHIDRA_SRC_DIR}